Coherency for write-back cache in a system designed for write-th

Details Coherency for write-back cache in a system designed for write-th Coherency for write-back cache in a system designed for write-th

1995-06-29

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711142, 711121, G06F 1208

Patent

active

058601112

ABSTRACT:
A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.

REFERENCES:
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5463759 (1995-10-01), Ghosh

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