Coherency for write-back cache in a system designed for write-th

Details Coherency for write-back cache in a system designed for write-th Coherency for write-back cache in a system designed for write-th

1993-11-12

1997-09-02

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711135, 711143, G06F 1200

Patent

active

056641494

ABSTRACT:
A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

REFERENCES:
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5319766 (1994-06-01), Thaller et al.

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