Coherence-free cache

Details Coherence-free cache Coherence-free cache

2006-05-23

2006-05-23

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S145000, C711S130000

Reexamination Certificate

active

07051164

ABSTRACT:
The present invention relates to a cache (10) and system and method of maintaining cache coherency in a parallel processing system, by tagging (13) cached data (11) with the identity of the users or process threads which have access rights to the data. Cache users may see a cache miss even if the data is in the cache, unless they have access rights. The tags can be reset to disallow further access on thread transfer or at the point of synchronisation of process threads.

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