Coherence apparatus for cache of multiprocessor

Details Coherence apparatus for cache of multiprocessor Coherence apparatus for cache of multiprocessor

1996-02-07

1999-03-30

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711120, 711147, G06F 1300

Patent

active

058902171

ABSTRACT:
A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

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