Coefficient generation apparatus for variable length decoder

Details Coefficient generation apparatus for variable length decoder Coefficient generation apparatus for variable length decoder

1993-05-17

1994-11-29

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

To or from bit count codes

341 67, H03M 746

Patent

active

053694058

ABSTRACT:
A coefficient generation apparatus for a variable length decoder, capable of simplifying its circuit arrangement and reducing a processing time required to decode run-length signals and thus recover them to have actual coefficients. The apparatus comprises an absolute address generation circuit for generating an absolute address, based on a run signal from a run/level decoder, a memory control circuit for outputting the run signal of the run/level decoder and an output signal of the absolute address generation circuit and controlling outputting of a level from the run/level decoder, a first-in and first-out (FIFO) memory for storing the level and address outputted from the memory control means, and a coefficient generation circuit for outputting required level at addresses whose level values are transferred and zero at the remaining addresses, based on the run value from the FIFO memory, and thus generating a predetermined number of coefficients per block.

REFERENCES:
patent: 4499498 (1985-02-01), Iinuma
patent: 4591829 (1986-05-01), Takeda
patent: 4596039 (1986-06-01), Mitchell et al.
patent: 4811113 (1989-03-01), Ozeki et al.
patent: 4971407 (1990-11-01), Hoffman
patent: 5060242 (1991-10-01), Arbeiter

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