Boots – shoes – and leggings
Patent
1994-03-11
1997-09-09
Eng, David Y.
Boots, shoes, and leggings
364948, 3642631, G06F 924
Patent
active
056665059
ABSTRACT:
A heuristic prefetch mechanism that fetches code without solicitation by the execution unit. The prefetch mechanism is configured to normally prefetch sequential code and, if a particular line of requested code is out of sequence with respect to an immediately preceding line of requested code, is configured to store in a memory tag unit the address of the previous instruction along with the subsequently requested out-of-sequence address. If the execution unit later issues another request for the previous instruction, the prefetch mechanism prefetches the corresponding out-of-sequence address stored in the memory tag unit. During each instruction fetch, a comparison is made to determine whether that particular instruction has been stored within the memory tag unit. If the memory tag unit has stored a non-sequential address corresponding to a requested instruction, the non-sequential address is loaded into a prefetch address latch. If no corresponding entry is in the memory tag unit, the address sequential to the requested address is stored within the prefetch address latch. A memory fetch unit subsequently prefetehes the line corresponding to the address within the prefetch address latch and stores the line within a buffer. During each instruction fetch by the CPU core, the memory fetch unit determines whether the requested instruction resides within the buffer and, if present, may provide the code directly.
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Advanced Micro Devices , Inc.
Eng David Y.
Kivlin B. Noel
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