Coding of FPGA and standard cell logic in a tiling structure

Details Coding of FPGA and standard cell logic in a tiling structure Coding of FPGA and standard cell logic in a tiling structure

2006-07-18

2006-07-18

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C717S141000, C717S142000, C717S143000, C717S144000, C717S136000

Reexamination Certificate

active

07080344

ABSTRACT:
A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

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patent: 2003/0149954 (2003-08-01), McElvain et al.

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