Coding apparatus and coding method

Details Coding apparatus and coding method Coding apparatus and coding method

2011-08-30

2011-08-30

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S701000

Reexamination Certificate

active

08010870

ABSTRACT:
The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder13integrates the product of an information word D13of six bits supplied from a cyclic shift circuit12and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15to a RAM14. The RAM14stores the sum D15. Further, the RAM14successively reads out sums D16of 2 bits stored already therein and supplies the read out sums D16as sums D17to an accumulator16through an interleaver15. The accumulator16integrates the sums D17and outputs a sum D18obtained as a result of the integration as a parity bit p of a codeword c through a selector17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.

REFERENCES:
patent: 6633856 (2003-10-01), Richardson et al.
patent: 6757122 (2004-06-01), Kuznetsov et al.
patent: 6895547 (2005-05-01), Eleftheriou et al.
patent: 6898248 (2005-05-01), Elgamal et al.
patent: 7181676 (2007-02-01), Hocevar
patent: 7260763 (2007-08-01), Sukhobok et al.
patent: 7313752 (2007-12-01), Kyung et al.
patent: 7349478 (2008-03-01), Lakkis
patent: 7395494 (2008-07-01), Lee et al.
patent: 7406647 (2008-07-01), Lakkis
patent: 7415061 (2008-08-01), Currivan et al.
patent: 7543212 (2009-06-01), Miles et al.
patent: 2005/0278604 (2005-12-01), Yokokawa et al.
patent: 2004-364233 (2004-12-01), None
patent: 2005-051461 (2005-02-01), None
patent: WO 2004/019268 (2004-03-01), None
patent: WO 2004/102811 (2004-11-01), None
patent: WO 2006/020460 (2006-02-01), None
patent: WO 2006/055249 (2006-05-01), None
Search Report in European Application No. EP 06 74 5483 (Mar. 22, 2010).
R. Echard et al., “The π-Rotation Low-Density Parity Check Codes,” Proc. IEEE Global Telecommunications Conference, GlobeCom 2001, pp. 980-984 (Nov. 25, 2001).
D. Haley et al., “Iterative Encoding of Low-Density Parity-Check Codes,” Proc. IEEE Global Telecommunications Conference, GlobeCom 2002, vol. 2, pp. 1289-1293 (Nov. 17, 2002).

Affiliated with

Also associated with

Rating

Coding apparatus and coding method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Coding apparatus and coding method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coding apparatus and coding method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2764299