Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
1999-11-04
2002-11-12
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C710S005000, C710S052000, C348S416100
Reexamination Certificate
active
06480908
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88111570, filed Jul. 8, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system technology, and more particularly, to a codec (coder/decoder) system including two or more codecs, which allows all the codecs to know the operating status of each other so that system crash can be prevented during a power down/suspend operation.
2. Description of Related Art
FIG. 1A
is a schematic diagram showing a codec system including a codec
12
and a codec controller
10
which are designed in compliance with the AC
97
standard. As shown, the signal lines between the codec controller
10
and the codec
12
are nominated as RESET#, BIT_CLK, SYNC, SDATA_IN, and SDATA_OUT; wherein the RESET#, SYNC, and SDATA_OUT signals are transferred from the codec controller
10
to the codec
12
, while the BIT_CLK and SDATA_IN signals are transferred from the codec
12
to the codec controller
10
.
FIG. 1B
is a signal timing chart showing the waveforms and timings of the SYNC, BIT_CLK, and SDATA_OUT signals transferring between the codec controller
10
and the codec
12
shown in FIG.
1
A. As shown, at the temporal point T
0
, the SYNC signal starts to rise from logic low state to logic high state; and during the rising of the SYNC signal, the BIT_CLK signal is switched from low-voltage logic state to high-voltage logic state. Sub-sequently, at the temporal point T
1
, the codec controller
10
starts to send out the valid frame F of the SDATA_OUT signal to the codec
12
. This signal sequencing scheme is in compliance with the ACLINK protocol.
FIG. 2
shows a codec system including an ACLINK-compliant codec controller
20
and two codecs: an audio codec (CODEC
0
)
22
and a modem codec (CODEC
1
)
24
, which are incorporated in a computer system. In accordance with the ACLINK protocol, the ACLINK-compliant codec controller
20
is interconnected with the audio codec
22
and the modem codec
24
in such a manner that the BIT_CLK signal line is driven by the audio codec
22
; the SDATA_OUT signal line is shared by both the audio codec
22
and the modem codec
24
; and the audio codec
22
utilizes the SDATA_IN
0
signal line while the modem codec
24
utilizes the SDATA_IN
1
signal line for transferring data to the ACLINK-compliant codec controller
20
.
One drawback to the foregoing codec system of
FIG. 2
, however, is that the audio codec
22
and the modem codec
24
are incapable of knowing the operating status of each other. This drawback can easily cause the codec system to crash when the codec system is entering the Power Down/Suspend Mode. This is because that at the start of this mode, the audio codec
22
will disable the BIT CLK signal; and at this time, if the modem codec
24
is still in active operation, the disabling of the BIT_CLK signal will cause the modem codec
24
to not work, and therefore result in a crash to the overall codec system.
The foregoing problem is particularly serious in the case where the functions of audio, modem, communications, and graphics are integrated in a single chip. There exists, therefore, a need for a codec system which allows all the codecs to know the operating status of each other so that system crash can be prevented when entering the Power Down/Suspend Mode.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a codec system, which allows all the codecs therein to know the operating status of each other so that the codec system can be prevented from system crash when entering the Power Down/Suspend Mode.
It is another object of this invention to provide a codec system, in which the codec used to generate the clock signal will be disabled only when all the other codecs are in inactive operation.
It is still another object of this invention to provide a codec system, which can enter into the Power Down/Suspend Mode operation only when all the codecs in the codec system are in inactive operation.
In accordance with the foregoing and other objects, the invention provides a codec system with shadow buffers and a method of performing a Power Down/Suspend Mode operation on this codec system.
The codec system of the invention includes: a first codec; a second codec; a first codec controller, coupled to the first codec, for controlling the operation of the first codec; the first codec controller including a first status data buffer and a first shadow buffer; and a second codec controller, coupled to the second codec, for controlling the operation of the second codec; the second codec controller including a second status data buffer and a second shadow buffer. The first codec controller utilizes the first status data buffer for registering the operating status thereof; and the second codec controller utilizes the second status data buffer for registering the operating status thereof. Moreover, the first codec controller utilizes the first shadow buffer for storing a copy of the operating status data stored in the second status data buffer of the second codec controller; and the second codec controller utilizes the second shadow buffer for storing a copy of the operating status data stored in the first status data buffer of the first codec controller.
In the foregoing codec system, for instance, the first codec is an audio codec, while the second codec is a modem codec, and the associated codec controllers are in compliance with the ACLINK protocol. The invention allows all the codecs therein to know the operating status of each other without having to do it through the ACLINK-compliant controllers.
Further, the method of the invention for performing a Power Down/Suspend Mode operation on the foregoing codec includes the following procedural step: (1) registering the operating status of each codec controller in its status data buffer, and meanwhile making a copy of the registered status data in the shadow buffer of each of the other codec controllers; (2) during operation, setting the active bit in the status data buffer of each codec controller to a first value (for example, the binary value 1) indicative of active operation and a second value (for example, the binary value 0) indicative of inactive operation; and (3) when Power Down/Suspend Mode is requested, checking whether all the active bits are set to the second value; if YES, switching the codec system to the Power Down/Suspend Mode.
By the invention, all the codecs in the codec system are capable of knowing the operating status of each other, and the codec that is responsible for generating the BIT_CLK signal will disable the BIT_CLK signal only when it checks that all the other codecs are inactive. This feature can help prevent system crash that would otherwise occur in the case of the prior art.
REFERENCES:
patent: 5619252 (1997-04-01), Nakano
patent: 5703651 (1997-12-01), Kim et al.
patent: 5883670 (1999-03-01), Sporer et al.
patent: 6035349 (2000-03-01), Ha et al.
patent: 6195766 (2001-02-01), Maxwell et al.
patent: 6259957 (2001-07-01), Alexander et al.
patent: 6389033 (2002-05-01), Maxwell et al.
patent: 6418203 (2002-07-01), Marcie
Chen Yung-Hui
Han Chia hui
Pan Benjamin Ym
Gaffin Jeffrey
J.C. Patents
Mai Rijue
Via Technologies Inc.
LandOfFree
Codec system with shadow buffers and method of performing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Codec system with shadow buffers and method of performing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Codec system with shadow buffers and method of performing a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2941205