Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-04-13
2002-11-12
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S265000
Reexamination Certificate
active
06480983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a code state determining method and an encoding apparatus that encodes spectral-null type trellis code for example DC-free code or Nyquist-free code used for a magnetic recording/reproducing apparatus, a magneto-optical disc apparatus, or the like that stores computer data.
2. Description of the Related Art
Next, with reference to
FIG. 1
, a signal process system for use with a conventional recording/reproducing apparatus will be described. Input data is supplied to an m
encoder
11
. The m
encoder
11
converts the input data into code with a relation of m:n (where m is the bit length of non-encoded data; and n is the bit length of encoded data). The m
encoder
11
supplies the resultant code to an D/A converter
12
. The D/A converter
12
converts the code received from the m
encoder
11
into a record square wave. The record square wave is supplied to a recording/reproducing circuit
13
. The recording/reproducing circuit
13
drives for example a magnetic head or an optical pickup (not shown) so as to record data to a record medium such as a magnetic disc or a magneto-optical disc.
On the other hand, a signal reproduced from a record medium by the magnetic head or the optical pickup is supplied to an analog equalizer
14
. The analog equalizer
14
equalizes the reproduced signal into a signal with a particular equalized characteristic. The resultant signal is supplied to an A/D converter
15
. The A/D converter
15
converts the output signal of the analog equalizer
14
into a digital signal. The digital signal is supplied to a code detector
16
. The code detector
16
detects code from the output signal of the A/D converter
15
. The resultant signal is supplied to an n/m decoder
17
. The n/m decoder
17
converts the output signal of the code detector
16
into a signal with a relation of n:m. When the analog equalizer
14
does not sufficiently equalize the output signal of the recording/reproducing circuit
13
, a digital equalizer may be disposed between the A/D converter
15
and the code detector
16
. In recent years, a maximum likelihood detector has been commonly used as the code detector
16
.
The code used in the recording/reproducing system is designed corresponding to a predetermined state transition diagram. Thus, when there are a plurality of states of start points and end points of code, it is necessary to determine the states of end points of individual code words that are successively encoded.
Next, with reference to
FIG. 2
, a more practical structure of the m
encoder
11
shown in
FIG. 1
will be described in the case that the m
encoder
11
performs an 8/10 code conversion of which the number of states of start points and end points of code is two. Eight-bit parallel data abcdefgh is input to an 8/10 encoder
21
. The 8/10 encoder
21
converts the eight-bit parallel data abcdefgh into 10-bit code ABCDEFGHIJ. The 10-bit code ABCDEFGHIJ is supplied to a downstream circuit for example the D/A converter
12
shown in FIG.
13
. In addition, the 10-bit code ABCDEFGHIJ is supplied to a state determining circuit
22
.
The state determining circuit
22
determines the states of end points of code. The state determining circuit
22
generates one-bit code X represents one of two states of each end point of code. The one-bit code X is supplied to an 8/10 encoder
21
. With reference to the one-bit code X, the 8/10 encoder
21
successively generates 10-bit code.
Example of code that is used for such an encoder are spectral-null type trellis codes (such as DC-free code and Nyquist-free code), RLL (Run Length Limited) code, MTR (Maximum Transition Run) code. In DC-free code, DSV (Digital Sum Value) that is an amplitude value of an accumulated charge such as DC accumulated charge RDS (Running Digital Sum) or the like is restricted to a limited value so that a DC component of the code spectrum on the frequency axis becomes null.
On the other hand, in Nyquist-free code, ASV (Alternating Digital Sum Value) that is am amplitude value of an AC accumulated charge ADS (Alternating Digital Sum) is restricted to a limited value so that a Nyquist frequency component of the code spectrum on the frequency axis becomes null. Conventionally, in many types of tape storage systems such as a digital audio tape recorder (R-DAT) and an 8-mm advanced intelligent tape system (AIT), 8/10 conversion DC-free code whose DSV is six has been widely used.
On the other hand, in RLL code, the maximum number of successive “0s” of pre-NRZI-modulated code is limited (constant). In MTR code, the maximum number of successive “1s” of pre-NRZI-modulated code is limited (constant).
With respect to RLL code or MTR code of which only the maximum number of successive “1s” or “0s” is defined, the state can be easily determined by counting the number of successive “1s” or “0s” after an end point of code. On the other hand, in spectral-null type trellis code such as DC-free code or Nyquist-free code, it is not easy to determine the state of an end point of code.
FIG. 3
is a flow chart showing an example of the structure of a state determining circuit used in an encoding apparatus that encodes 8/10 conversion DC-free code. An example of such a state determining circuit has been disclosed by S. Fukuda, Y. Kojima, Y. Shinpuku, and K. Okada, “8/10 Modulation Codes for Digital Magnetic Recording, IEEE Trans. on Magn. vol. MAG-22, No. 5, pp. 1194-1196, September 1986”. The circuit is composed of five EXOR (Exclusive Or) circuits
31
,
32
,
33
,
34
and
35
and one flip-flop
36
. Assuming that one EXOR circuit is composed of three gates and that one flip-flop is composed of eight gates, the state determining circuit is composed of around 23 gates.
In the structure shown in
FIG. 3
, states are determined corresponding to only odd bits A, C, E, G, and I. The structure is accomplished due to the following fact that was discovered with respect to two-state DC-free code. In other words, in two-state DC-free code, when the value of {mod
2
(sum of odd bits of code)} is 0, a state inversion takes place.
FIG. 4
is a schematic diagram showing an example of a state transition diagram for generating 8/10 conversion DC-free code. The state transition diagram has six states (DSV=6) of code that is NRZI modulated. In the conventional 8/10 conversion DC-free code, as shown in
FIG. 4
, states of end points and start point of code are state
2
or state
3
.
DC-free code whose each bit is inverted from “0” to “1” or vice versa is Nyquist-free code. Thus, with respect to DC-free code and Nyquist-free code, code can be generated and determined using almost similar method.
As described above, in an example of the conventional two-state 8/10 conversion DC-free code, the state of an end point of code can be determined corresponding to the sum of odd bits. However, such a method has been accomplished by a discovery approach. Thus, the method cannot be generally applied to spectral-null code such as DC-free code or Nyquist free-code.
On the other hand, when the number of states of end points and start points of code words is increased from two to three or four, since the number of code words that can be generated increases, the encoding efficiency of available code may improve. However, if the state determination of such code is performed by hardware, the number of bits of a signal that represents determined states increases. In other words, when the number of states of end points and start points of code is two, the number of bits of the signal that represents the determined states is one. On the other hand, when the number of states of end points and start points of code is three or four, the number of bits of the signal that represents determined results becomes two. Thus, the structure of the state determining circuit becomes complicated.
So far, various converting methods including a method of which the number of states of start points and end points of code is three have been proposed. However, abo
De'cady Albert
Sony Corporation
Torres Joseph D.
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