Code sequence for vector gather and scatter

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses

Reexamination Certificate

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C711S220000, C712S004000, C712S005000, C712S225000

Reexamination Certificate

active

07093102

ABSTRACT:
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector gather and scatter operations. By contrast, one embodiment of the present invention implements gather and scatter operations using a plurality of deposit and extract instructions. As a result, gather and scatter operations may be efficiently performed within a general purpose processing environment and without the need for dedicated gather/scatter hardware.

REFERENCES:
patent: 2968027 (1961-01-01), McDonnell et al.
patent: 3163850 (1964-12-01), Austin et al.
patent: 3395397 (1968-07-01), King
patent: 3973244 (1976-08-01), Lovercheck et al.
patent: 5008786 (1991-04-01), Thatte
patent: 5206822 (1993-04-01), Taylor
patent: 5895501 (1999-04-01), Smith
IBM, “Overlapped Peripheral Block Transfer Unit”, May 1966, IBM Technical Disclosure Bulletin, vol. 8, Issue 12, pp. 1734-1735.
“Pipelined Computers”, Parallel Computers, RW Hockney and CR Jesshope, 1981, pp. 73-93.

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