Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2006-08-15
2006-08-15
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S220000, C712S004000, C712S005000, C712S225000
Reexamination Certificate
active
07093102
ABSTRACT:
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector gather and scatter operations. By contrast, one embodiment of the present invention implements gather and scatter operations using a plurality of deposit and extract instructions. As a result, gather and scatter operations may be efficiently performed within a general purpose processing environment and without the need for dedicated gather/scatter hardware.
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Padmanabhan Mano
Walter Craig E
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