Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-12-23
2004-01-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S052000
Reexamination Certificate
active
06678858
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a code error monitor apparatus for monitoring a code error generated in data transmitted through a transmission line (for example, data bus) More specifically, this invention relates to a code error monitor apparatus which can be suitably used for a transmission line that adopts two different types of systems for detecting a code error.
BACKGROUND OF THE INVENTION
In recent years, with an increase in the data processing speed in an information processing apparatus an amount of data in a transmission line such as a data bus is also increasing remarkably. When the amount of data to be transmitted increases a code error becomes a problem. Accordingly, in a conventional manner, in order to detect a code error, an error correcting code (a redundant bit) is added to the data to be transmitted so that the code error is detected by the code error detecting systems such as a known odd parity check system and even parity check system, and thus the code error is corrected.
In addition, in a computer system, a CPU (Central Processing Unit) is connected with a apparatus (memory, display, etc.) to be controlled by a system bus composed of a plurality of buses, and occasionally different code error detecting systems are adopted for each bus. In such a system also it is required to suppress a rate of generation of malfunction due to a code error as low as possible.
FIG. 28
is a block diagram showing a structure of the main sections of a conventional code error monitor apparatus. The code error monitor apparatus shown in
FIG. 28
detects a code error in data to be transmitted through a data bus according to two different code error detecting systems, and corrects the code error based on the detected results. In
FIG. 28
, a data bus
1
A on the CPU side transmits bit data DATA_A[
0
] through bit data DATA_A[n] of (n+1) bits, and its one end is connected with a not shown CPU.
In addition, the data bus
1
A on the CPU side is provided with a data line for transmitting A-system error correcting code DP_A. The A-system error correcting code DP_A is a redundant bit for detecting a code error in bit data DATA_A[
0
] through bit data DATA_A[n] according to a system A (for example, odd parity check system). In this odd parity check system, A-system error correcting code DP_A of “1” or “0” is added as a redundant bit to a bit string of (n+1) bits composed of the bit data DATA_A[
0
] through bit data DATA_A[n] so that a number of “1” becomes an odd number in the bit data DATA_A[
0
] through bit data DATA_A[n] and in A-system error correcting code DP_A.
That is, in the odd parity check system, when the number of “1” in the bit string of (n+1) bits is an even number, the A-system error correcting code DP_A of “1” is added to the bit string. On the other hand, when the number of “1” in the bit string of (n+1) bits is an odd number, A-system error correcting code DP_A of “0” is added to the bit string. The bit string composed of ((n+1)+1) bits where the A-system error correcting code DP_A is added to the bit data DATA_A[
0
] through bit data DATA_A[n] is referred to as an A-system bit string in the following description.
One end of an internal data bus
1
B is connected with the data bus
1
A on the CPU side, and the other end is connected with a not shown apparatus (for example, memory) to be controlled. That is, the data bus
1
A on the CPU side and the internal data bus
1
B form a data bus which connects the CPU and the apparatus to be controlled. The internal data bus
1
B transmits the bit data DATA_A[
0
] through bit data DATA_A[n] transmitted on the data bus
1
A on the CPU side as bit data DATA_B[
0
] through bit data DATA_B[n] to the apparatus to be controlled.
That is, similarly to the data bus
1
A on the CPU side, the internal data bus
1
B transmits bit data DATA_B[
0
] through bit data DATA_B[n] of (n+1) bits. Moreover, the internal data bus
1
B is provided with a data line for transmitting a B-system error correcting code DP_B. The B-system error correcting code DP_B is a redundant bit for detecting a code error in the bit data DATA_B[
0
]) through bit data DATA_B[n] according to a system B (for example, even parity check system).
In this even parity check system, the B-system error correcting code DP_B of “1” or “0” is added as a redundant code to the bit string of (n+1) bits composed of the bit data DATA_B[
0
] through bit data DATA_B[n] so that a number of “1” in the bit data DATA_B[
0
] through bit data DATA_B[n] and in the B-system error correcting code DP_B becomes an even number.
That is, in the even parity check system, when “1” in the bit string of (n+1) bits is an odd number, the B-system error correcting code DP_B of “1” is added to the bit string. On the other hand, when a number of “1” in the bit string of (n+1) bits is an even number, the B-system error correcting code DP_B of “0” is added to the bit string. The bit string composed of ((n+1)+1) bits where the B-system error correcting code DP_B is added to the bit data DATA_B[
0
] through bit data DATA_B[n] is referred to as a B-system bit string in the following description.
Thus, in the data bus composed of the data bus
1
A on the CPU side and the internal data bus
1
B, two different types of code error detecting systems: the system A (odd parity check system) and the system B (even parity check system) are adopted. A A-system code error detecting circuit
2
detects a code error based on the number of “1” in the A-system bit string (bit data DATA_A[
0
] through bit data DATA_A[n] and A-system error correcting code DP_A) according to the system A (odd parity check system).
More specifically, when the number of “1” in the A-system bit string is an even number then the A-system code error detecting circuit
2
judges that a code error has occurred in the data bus
1
A on the CPU side and outputs an A-system code error detecting signal ERROR_A of “1” to the CPU. On the other hand, when the number of “1” in the A-system bit string is an odd number then the A-system code error detecting circuit
2
judges that a code error has not occurred in the data bus
1
A on the CPU side and outputs an A-system code error detecting signal ERROR A of “0” to the CPU.
A B-system error correcting code generating circuit
3
is provided on a downstream side of the A-system code error detecting circuit
2
, and generates a B-system error correcting code DP_B of “1” or “0” so that the number of “1” in the bit string of (n+2) bits composed of the bit data DATA_A[
0
] through bit data DATA_A[n] and the B-system error correcting code DP_B becomes an even number. A B-system code error detecting circuit
4
is provided on a downstream side of the B-system error correcting code generating circuit
3
. This B-system code error detecting circuit
4
detects a code error based on the number of “1” in the B-system bit string (bit data DATA_B[
0
] through bit data DATA_B[n] and B-system error correcting code DP_B) according to the system B.
More specifically, when the number of “1” in the B-system bit string is an odd number then the B-system code error detecting circuit
4
judges that a code error has occurred in the internal data bus
1
B and outputs a B-system code error detecting signal ERROR_B of “1” to the CPU. On the other hand, when the number of “1” in the B-system bit string is an even number then the B-system code error detecting circuit
4
judges that a code error has not occurred in the internal data bus
1
B and outputs a B-system code error detecting signal ERROR_B of “0” to the CPU.
In addition, in the conventional code error monitor apparatus, a code error is detected according to the system A on an upstream side of a poin
Britt Cynthia
De'cady Albert
Fujitsu Limited
Staas & Halsey , LLP
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