Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-09-08
2004-03-02
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S718000, C714S763000
Reexamination Certificate
active
06701468
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a code error correcting circuit for and a code error correcting method of interleaving the digital data. The present invention also relates to a communicating apparatus and a communicating method, which respectively include the code error correcting circuit and the code error correcting method.
2. Description of the Related Art
As a code error correcting technique for digital data, an interleave is performed. In the technical field of information communication, the bit arrangements of original data to be transmitted are permuted under a predetermined rule (i.e., interleaved) and the original data is transmitted at a transmitting side. Then, the original data is obtained or recovered by de-interleaving the received data under the predetermined rule at a receiving side. As the information communication is performed by using such an interleave, even if code errors are generated in the data by the influence of noises etc., the spots of the code errors are dispersed at the time of interleaving. Therefore, the spots of the code errors can be easily corrected, so that the communication quality can be improved.
Further, the interleave is utilized in not only the field of information communication but also the field of digital information process widely. As one example, the interleave is utilized at the time of recording data onto an information record medium such as a DVD or the like.
In order to perform the interleave, a semiconductor memory is prepared, which is accessible by a width of one bit. The data, in which the bit arrangements are permuted, are generated by writing respective bit data of the original data to a plurality of bits provided in the semiconductor memory and then reading out the written data one bit by one bit while memory-accessing in accordance with a predetermined order. The writing control to write the original data one bit by one bit into the semiconductor memory and the reading control to read out the written data one bit by one bit are performed by a microprocessor or a CPU (Central Processing Unit).
However, if the bit arrangements of the original data are permuted by using the above mentioned semiconductor memory which is memory-accessible by the one bit width, the number of times of memory-accessing for writing and reading the data into and from the semiconductor memory is certainly increased. Thus, there is a problem that a processing time duration required for interleaving becomes long and an enormous process burden is applied onto the microprocessor.
In an electronic apparatus such as a communicating apparatus, an information processing apparatus or the like which is provided with a microprocessor to operate, the data to be processed are treated as data of 2
n
(n: natural number) bits e.g., 8 bits, 16 bits, 32 bits and so on. Thus, as the working memory of the microprocessor, the semiconductor memory for storing the data of 2
n
bits in correspondence with respective addresses is used in general. Therefore, if the working memory is used at the time of interleaving, the resources equipped in the electronic apparatus may be efficiently utilized, and it may be convenient for the process of interleaving by the microprocessor.
However, in case that the interleave by the microprocessor is to be performed by using the above mentioned working memory, the original data are stored one bit by one bit into the respective memory areas of the working memory, and the stored data are read out one bit by one bit from the respective memory areas in accordance with the predetermined order. Thus, although the data of 2
n
bits can be stored in each memory area, only one bit is actually stored in each memory area, which causes a problem that the working memory cannot be efficiently utilized.
Furthermore, in case of using the above mentioned working memory, processes are repeated in which the bit data is stored as memory-accessing is performed by the unit of one bit to the respective memory areas and then the bit data is read out as memory-accessing is performed again by the unit of one bit to the respective memory areas in accordance with the predetermined order. Thus, in the same manner as using the conventional semiconductor memory accessible by the width of one bit, the number of times of memory-accessing is certainly large, so that the burden on the microprocessor becomes heavy and the processing time duration required for interleaving cannot be actually shortened, which is a problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a code error correcting circuit and a code error correcting method, which can perform interleaving at a high speed, by using of a memory device having a plurality of memory areas each storing data of 2
n
bits in association with each address, and which are suitable for interleaving under a control of a microprocessor, as well as a communicating apparatus and a communicating method, which respectively include the code error correcting circuit and the code error correcting method.
The above object of the present invention can be achieved by a code error correcting circuit for interleaving original data comprising a sequence of bit data having a length of p bits (p: natural number) by arranging the bit data of the original data into a hypothetical matrix of I (I: natural number not less than 2) rows and J (J: natural number not less than 2) columns and then selecting the bit data positioned on the i
th
(i: natural number, 1≦i≦I) row along an order of the j
th
(j: natural number, 1≦j≦J) column. The code error correcting circuit is provided with: a memory unit having a plurality of memory areas each having a length of 2
n
bits (n: natural number); a controller for storing the original data to be interleaved into the memory areas respectively; a first data generating device for generating a first data indicating a position of the i
th
row in the hypothetical matrix; a second data generating device for generating a second data indicating a position of the j
th
column in the hypothetical matrix; an address decoding device for generating address data indicating one of the memory areas, in which the bit data positioned on the j
th
column are stored, on the basis of the first data and the second data; and a select data decoding device for generating a bit select data indicating the bit data positioned on the i
th
row among the bit data stored in said one of the memory areas, which is indicated by the address data, on the basis of the first data and the second data. The controller controls the first data generating device, the second data generating device, the address decoding device and the select data decoding device so that the bit data, which are indicated by the bit select data, stored in the memory unit are sequentially outputted along an order of the i
th
row and the j
th
column in the hypothetical matrix as the interleaved original data.
According to the code error correcting circuit of the present invention, it is possible to interleave the original data by using the memory unit having the memory areas each having the length of 2
n
bits such as 8 bits, 16 bits, 32 bits and so on. Thus, it is possible to realize the code error correcting circuit suitable for a microcomputer system. Further, it is possible to reduce the number of times of memory-accessing the memory unit in case of employing the microprocessor. By this, it is possible to reduce the burden on the microprocessor while shortening the processing time duration required for interleaving.
In one aspect of the code error correcting circuit of the present invention, the code error correcting circuit is further provided with: a data holding device for holding the sequence of the bit data having a length of 2
n
bits, which are read out from the memory area corresponding to the address data; and a bit selecting device for selecting the bit data indicated by the bit select data from among the sequence of the bit data having the length of 2
n
Akimoto Takayuki
Kodama Yasuteru
Nohara Manabu
Odagawa Satoshi
Okamura Masahiro
Abraham Esaw T
Chung Phung M.
Morgan & Lewis & Bockius, LLP
Pioneer Corporation
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