Code error correcting apparatus

Details Code error correcting apparatus Code error correcting apparatus

1999-07-16

2002-02-05

Moise, Emmanuel L. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S769000

Reexamination Certificate

active

06345374

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a code error correcting apparatus and, more particularly, to a code error correcting apparatus that performs error correction on digital data read from a recording medium using an error correction code.
In compact disc read only memory (CD-ROM) systems, a digital audio CD is used as a read only memory (ROM) for storing digital data. To improve the reliability of digital data read from a CD, error correction is performed twice on the digital data. The first error correction is executed by a digital signal processor which is common to both an audio system and a CD-ROM system, and the second error correction is executed by a CD-ROM decoder of the CD-ROM system.
FIG. 1
is a schematic block diagram of a conventional CD-ROM system. The CD-ROM system includes a pickup
1
, a pickup controller
3
, an analog signal processor
4
, a digital signal processor
5
, a CD-ROM decoder
6
, a buffer random access memory (RAM)
7
and a control microcomputer
8
.
The pickup
1
irradiates light on a disc
2
to generate a voltage signal proportional to the intensity of the reflected light. The pickup controller
3
controls the read position of the pickup
1
with respect to the disc
2
so that the pickup
1
reads data from the disc
2
in the correct order. Servo control (CLV (constant linear velocity) control) to turn the disc
2
at a predetermined velocity is performed in accordance with the position control of the pickup
1
. The servo control maintains the linear velocity of tracks on the disc
2
constant. Another servo control (CAV (constant angular velocity) control) is also performed.
The analog signal processor
4
receives the voltage signal from the pickup
1
and generates one frame of an Eight to Fourteen Modulation (EFM) data signal consisting of 588 bits. As shown in
FIG. 2
, the EFM data includes a 24-bit sync signal assigned to the beginning of each frame, 3-bit connection bit fields and 14-bit data bit fields which are alternately provided in each frame after the sync signal.
The digital signal processor
5
receives the EFM signal from the analog signal processor
4
and performs EFM demodulation on the signal for conversion to 8 bits from 14 bits. In this EFM demodulation, 8-bit subcode data is produced from the first data bit field following the sync signal, and 32-byte symbol data is produced from the remaining thirty-two pieces of data bit fields. Further, the 32-byte symbol data is subjected to Cross-Interleave Reed-Solomon Code (CIRC) demodulation to yield one frame of CD-ROM data consisting of 24 bytes. The first error correcting process is completed with this CIRC demodulation.
The CD-ROM data is handled in a block by block manner, each block of data consisting of 2352 bytes (24 bytes×98 frames). As shown in
FIG. 3
, normally (in mode 1), one block of data includes a sync signal (12 bytes), a header (4 bytes), user data (2048 bytes), an error detection code (EDC) (4 bytes) and an error correction code (ECC) (276 bytes). In one block of data, 2340, excluding the 12-byte sync signal, have previously undergone a scrambling process and are reproduced by a descrambling process. This descrambling process is performed to prevent a pattern similar to a sync signal from entering into one block of data.
The CD-ROM decoder
6
receives the CD-ROM data from the digital signal processor
5
and performs error correction in accordance with the ECC and error detection in accordance with the EDC and then provides the processed CD-ROM data to a host computer. Normally, therefore, after an error in the data is corrected in accordance with the ECC, it is checked in accordance with the EDC to determine if the error was properly corrected. When the error has not been corrected properly, error correction is carried out again in accordance with the ECC, or an error flag is affixed to the CD-ROM data containing the error code.
The buffer RAM
7
is connected to the CD-ROM decoder
6
and temporarily stores the CD-ROM data in a block by block manner. Since the ECC and EDC are included in one block of CD-ROM data, the CD-ROM decoder
6
requires at least one block of CD-ROM data. Therefore, the buffer RAM
7
stores one block of CD-ROM data for the CD-ROM decoder
6
.
The control microcomputer
8
may be a one-chip microcomputer having an internal ROM and an internal RAM. The control microcomputer
8
controls the operation of the CD-ROM decoder
6
in accordance with a control program stored in the ROM. At the same time, the control microcomputer
8
receives command data from the host computer and subcode data from the digital signal processor
5
and temporarily stores the command and subcode data in the internal RAM. The control microcomputer
8
controls the operations of the individual circuits
3
,
4
,
5
,
6
in accordance with the command data (i.e., commands from the host computer) so that the host computer can receive the desired CD-ROM data from the CD-ROM decoder
6
.
The analog signal processor
4
, the digital signal processor
5
, the CD-ROM decoder
6
, the buffer RAM
7
, and the control microcomputer
8
respectively consist of independent integrated circuits. The CD-ROM decoder
6
receives the CD-ROM data from the digital signal processor
5
and serially outputs the CD-ROM data to the host computer. This allows the integrated circuits to have less input and output pins and makes the wiring configuration less complicated. For example, as shown in
FIG. 4
, the digital signal processor
5
transfers 16-bit CD-ROM data to the CD-ROM decoder
6
in order of MSB to LSB (or LSB to MSB). This data transmission is performed synchronously with a clock signal CK generated by the EFM signal. A channel identification signal LR which is inverted in response to the end of each data is also transferred synchronously with the CD-ROM data. The CD-ROM decoder
6
receives the CD-ROM data by detecting a rising edge and falling edge of the channel identification signal LR while identifying the position of the MSB or LSB of the CD-ROM data.
When the play back speed of the disc
2
is increased, the frequency of the EFM signal is increased and consequently the frequency of the clock signal CK is also increased. This affects the serial transmission of the CD-ROM data. That is, the high frequency clock signal CK causes a circuit operation delay of the digital signal processor
5
and a slight timing lag between the CD-ROM data and the clock signal CK. This timing lag makes it difficult the CD-ROM decoder
6
to receive the CD-ROM data correctly.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a code error correcting apparatus which transfers the CD-ROM data correctly.
In one aspect of the present invention, a code error correcting apparatus is provided that includes a digital processor for performing a predetermined process on digital data and generating an identification signal synchronized with the output timing of the digital data. A latch circuit is connected to the digital processor and latches a plurality of processed digital data in accordance with the identification signal. An input interface circuit is connected to the latch circuit and an external memory circuit, receives the plurality of processed digital data from the latch circuit and stores the plurality of digital data in the external memory circuit. A code error correcting circuit is connected to the external memory circuit, receives the plurality of processed digital data from the external memory circuit, performs a code error correction process on the plurality of digital data, and stores the corrected data back in the external memory circuit. An output interface circuit is connected to the external memory circuit and reads the plurality of corrected processed digital data from the external memory circuit. The digital processor, the latch circuit, the input interface circuit and the code error correcting circuit are integrated on a single semiconductor substrate.
Other aspects and advantages of the invention will become ap

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