Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-10-20
2004-01-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S769000
Reexamination Certificate
active
06675343
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a code error correcting and detecting apparatus, and, more particularly, to a code error correcting and detecting apparatus that corrects an error contained in digital data read from a recording medium, such as a CD (compact disc) or a DVD (digital video disc), and performs processing using an error-detecting code.
When a computer acquires digital data recorded on a recording medium, decode processing for correcting a code error contained in the digital data is performed using a drive system, such as a CD-ROM system. Since the decode processing is performed in units of sectors, each consisting of a predetermined number of bytes, the digital data is buffered in a memory in units of sectors.
FIG. 1
is a schematic block diagram of a conventional CD-ROM system
100
. Digital data that conforms to a predetermined format is recorded on a disc
1
along a spiral recording track. The disc
1
rotates so that a linear velocity or an angular velocity is maintained constant. A pickup
2
irradiates the surface of the disc
1
with laser light and reads the digital data recorded on the disc
1
in accordance with a variation of the reflected light. An analog signal processor
3
processes an analog output signal from the pickup
2
and generates an Eight to Fourteen Modulation (EFM) signal indicating the digital data. The EFM signal is generated by EFM-modulating 8-bit data. As shown in
FIG. 2
, for EFM data, the first 24 bits of one frame are assigned to a synchronous field, and a three bit connection field and a 14 bit data field are alternately assigned after the synchronous signal.
A digital signal processor
4
receives the EFM signal from the analog processor
3
, applies EFM demodulation to the EFM signal and, as shown in
FIG. 2
, converts the 14-bit data to 8-bit data. In the EFM demodulation, 1-byte of subcode data is fetched from the first data field after a synchronous signal and 32-bytes of symbol data are generated from the remaining data fields. The digital signal processor
4
applies CIRC decoding to the 32-bytes of symbol data and generates 24-bytes of CD-ROM data.
A CD-ROM decoder
5
receives the CD-ROM data from the digital signal processor
4
, performs a code error correction on the CD-ROM data and transfers the corrected CD-ROM data to a host computer in accordance with a request from the host computer. A buffer RAM
6
is connected to the CD-ROM decoder
5
and stores the CD-ROM data supplied from the digital signal processor
4
for a predetermined time. Since an Error-Correcting Code (ECC) and an Error-Detecting Code (EDC) are set for the one-sector CD-ROM data, at least one sector of CD-ROM data is stored in the buffer RAM
6
. Further, several sectors of error-corrected CD-ROM are stored in the buffer RAM
6
.
A control microcomputer
7
controls the analog signal processor
3
, the digital signal processor
4
and the CD-ROM decoder
5
using a predetermined operation program. The control microcomputer
7
controls the analog signal processor
3
, the digital signal processor
4
and the CD-ROM decoder
5
in accordance with a request from the host computer to transfer the CD-ROM data to the host computer.
FIG. 3
is a schematic block diagram of the CD-ROM decoder
5
. The CD-ROM decoder
5
comprises an input interface
11
, an error correction circuit
12
, an error detection circuit
13
, an output interface
14
and a memory interface
15
.
The input interface
11
receives 2,352 bytes of one block of CD-ROM data from the digital signal processor
4
and supplies the CD-ROM data to the memory interface
15
. The input interface
11
performs descramble processing on the CD-ROM data, except for a 12-byte synchronous signal and stores the descrambled CD-ROM data in the buffer RAM
6
.
The error correction circuit
12
receives the CD-ROM data stored in the buffer
6
in units of blocks and performs the code error correction processing on the CD-ROM data using the ECC every block. Erroneous CD-ROM data stored in the buffer RAM
6
is rewritten with correct data.
The error detection circuit
13
receives error-corrected CD-ROM data from the buffer RAM
6
in units of blocks and checks whether a code error is contained in the CD-ROM data using the EDC every block. If the error code is detected by the error detection circuit
13
, an error flag is added to the error -corrected CD-ROM data.
The output interface circuit
14
reads the processed CD-ROM data stored in the buffer RAM
6
in response to an instruction from the host computer and supplies the processed CD-ROM data to the host computer. The output interface circuit
14
receives control information from the host computer and supplies the control information to the control microcomputer
7
.
The memory interface
15
controls the input/output of CD-ROM data between the buffer RAM
6
and the input interface
11
, the error correction circuit
12
, the error detection circuit
13
and the output interface
14
in a time-division manner. That is, a plurality of the CR-ROM data cannot be written to and read from the buffer RAM
6
at the same time. Accordingly, the memory interface
15
assigns access from each circuit to the buffer RAM
6
in conformity with the operation of each circuit.
Error correction accuracy is improved by repeating code error correction processing by the error correction circuit
13
. For example, if P-parity code and Q-parity code are set regarding the ECC, an error contained in the data is decreased by increasing the number of repetitions of the correction processing which uses the P-parity code and the correction processing which uses the Q-parity code.
When code error correction processing is repeated, all of circuit operations are controlled in accordance with an instruction from the control microcomputer. Accordingly, repetition of the correction processing increases the burden on the control microcomputer, so that a delay occurs in the processing operation of each circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a code error correcting and detecting apparatus that reduces the burden on a control microcomputer when code error correction processing is repetitively performed.
In one aspect of the present invention, an apparatus for correcting and detecting a code error in digital data including an error correcting code and an error detecting code is provided. The apparatus includes an error correction circuit for performing error correction processing on the digital data using the error-correcting code and generating error-corrected digital data. An error detection circuit performs error detection processing on the error-corrected digital data using the error-detecting code and checks whether an error is included in the error-corrected digital data. A control circuit is connected to the error correction circuit and the error detection circuit to causes the error correction circuit to repeat the error correction processing on the digital data in accordance with the check result of the error detection circuit.
In another aspect of the present invention, a method for correcting and detecting a code error in digital data including an error correcting code and an error detecting code is provided. First, error correction processing on the digital data is performed using the error-correcting code to generate error-corrected digital data. Then, error detection processing on the error-corrected digital data is performed using the error-detecting code and checking whether an error is included in the error-corrected digital data. A repetitive operation setting command of the error correction processing is stored in a first register. The check result of the error detection processing is stored in a second register. The error correction processing is repeated when the setting command stored in the first register indicates repetitive operation and the check result stored in the second register indicates the presence of a code error.
REFERENCES:
patent: 6094465 (2000-07-01), Stein et al.
patent:
Suzuki Takayuki
Tsuda Hiroyuki
De'cady Albert
Fish and Richardson P.C.
Torres Joseph D.
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