Code and thread differential addressing via multiplex page maps

Details Code and thread differential addressing via multiplex page maps Code and thread differential addressing via multiplex page maps

2006-07-04

2006-07-04

An, Meng-Al T. (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Virtual machine task or process management

C711S002000, C711S006000

Reexamination Certificate

active

07073173

ABSTRACT:
Described is a system and method whereby processes may have multiple memory maps associated therewith to provide curtained memory and overcome other memory-related problems. Multiple maps are used to restrict memory access of existing code such as drivers, without changing that code, and without changing existing microprocessors. A thread of a process is associated with one memory map at a time, which by mapping to different memory locations, provides memory isolation without requiring a process switch. Memory isolation may be combined with controlled, closed memory map switching performed only by trusted code, to ensure that some protected memory is inaccessible to all but the trusted code (curtained memory). Map switching among multiple maps eliminates the need to change a process in order to access different memory, thereby allowing expanded memory addressing in a single process and isolating untrusted code run in process from certain memory of that process.

REFERENCES:
patent: 5727211 (1998-03-01), Gulsen
patent: 5729710 (1998-03-01), Magee et al.
patent: 6304973 (2001-10-01), Williams
Frailey et al. “Software Support for Modern Microprocessor Memory Systems.” Midcon Midwest Electron Show Dec. 12-14 1978, pp. 1-15.
Blumrich, et al. “Virtual-Memory-Mapped Network Interfaces.” Feb. 1995 IEEE Micro, pp. 21-28.
Tanner, Daniel J. “Clearing Up The Confusion: Virtual vs. Mapped Memory.” Computer Design, Oct. 1976, pp. 101-105.
Teller, et al. “Locating Multiprocessor TLBs at Memory.” Proceedings of 27thHawaii International Conference on Systems Sciences, Jan. 4-7, 1994, pp. 554-563.
Sznyter, et al. “A New Virtual-Memory Implementation for UNIX.” Usenix Association summer Conference Proceedings, Jun. 9-13, 1986, pp. 81-92.
Baskett, F. “Pascal and Virtual Memory in a Z8000 or MC6800 Based Design Station.” Compcon '80 VLSI: Ne Architectural Horizons, Feb 25-28, 1980, pp. 25-28.
Hulme, B.B. “Memory Management with the Z8000 Microprocessor.” Midcon Conference, Sep. 1-17, 1987, pp. 86-91.
Kaplinsky, Cecil. “Memory Access Paths: Hierarchies and Protection.” Wescon Conference 1984, pp. 1-7.
Kotz et al. “The Expected Lifetime of Single-Address-Space: Operating Systems.” Sigmetrics 94, pp. 161-170.
Kuei et al. “Efficient Index Generation for Compiling Two-Level Mappings in Data-Parallel Programs.” Journal of Parallel and Distributed Computing, vol. 60, No. 2, Feb. 2000, pp. 189-216.

Affiliated with

Also associated with

Rating

Code and thread differential addressing via multiplex page maps does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Code and thread differential addressing via multiplex page maps, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Code and thread differential addressing via multiplex page maps will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3541191