Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1998-07-17
2001-11-06
Fahmy, Wael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S621000, C257S774000
Reexamination Certificate
active
06313531
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming coaxial integrated circuitry interconnect lines, to integrated circuitry, and to other co-axial line formation.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically fabricated on a wafer which is subsequently tested and separated into individual dies or chips. Individual dies are then packaged. Packaged chips are then assembled together, typically on a printed circuit board (PCB), and electrically interconnected to perform a desired function. The electrical interconnection of separately fabricated chips generally takes place externally of the individual chips. While PCB techniques are useful for bringing together separately fabricated and assembled chips, doing so brings with it some problems which are not so easily overcome. For example, PCBs consume a large amount of physical space compared to the circuitry of the chips which are mounted to them. It is desirable to reduce the amount of physical space required by such PCBs. Further, assuring the electrical integrity of interconnections between chips mounted on PCBs is a challenge. Moreover, in certain applications, it is desirable to reduce the physical length of electrical interconnections between devices because of concerns with signal loss or dissipation and interference with and by other integrated circuitry devices.
A continuing challenge in the semiconductor industry is to find new, innovative, and efficient ways of forming electrical connections with and between circuit devices which are fabricated on the same and on different wafers or dies. Relatedly, continuing challenges are posed to find and/or improve upon the packaging techniques utilized to package integrated circuitry devices. As device dimensions continue to shrink, these challenges become even more important.
This invention arose out of concerns associated with improving the manner in which electrical connections are formed relative to integrated circuitry devices. More particularly, this invention arose out of concerns associated with improving the manner in which electrical interconnections are formed relative to the same or different wafers or dies. Yet, certain aspects of the invention are seen to be applicable outside of the semiconductor processing industry, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents.
SUMMARY OF THE INVENTION
Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. A semiconductive substrate is provided. In one aspect, an inner conductive coaxial line component is formed which extends through the substrate. An outer conductive coaxial line component and coaxial dielectric material are formed, with the coaxial dielectric material being formed operably proximate and between the inner and outer conductive coaxial line components. In a preferred implementation, the substrate includes front and back surfaces, and a hole is formed which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion. Conductive material is formed proximate at least some of the interior wall portion. In one implementation, the conductive material constitutes semiconductive material which is doped with a conductivity-enhancing impurity. In another implementation, the conductive material constitutes a layer of metal-comprising material which is formed within the hole. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. Conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.
In a preferred implementation, the inner conductive coaxial line component is formed by forming a first material within the hole. A second material is formed over the first material, with at least the second material being conductive. Subsequently, the substrate is exposed to conditions which are effective to cause the second material to replace the first material.
REFERENCES:
patent: 3982268 (1976-09-01), Anthony et al.
patent: 4394712 (1983-07-01), Anthony
patent: 4419150 (1983-12-01), Soclof
patent: 4440973 (1984-04-01), Hawkins
patent: 4595428 (1986-06-01), Anthony et al.
patent: 4610077 (1986-09-01), Minahan et al.
patent: 4776087 (1988-10-01), Cronin et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 4933743 (1990-06-01), Thomas et al.
patent: 4939568 (1990-07-01), Kato et al.
patent: 4977439 (1990-12-01), Esquivel et al.
patent: 5148260 (1992-09-01), Inoue et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5312765 (1994-05-01), Kanber
patent: 5317197 (1994-05-01), Roberts
patent: 5424245 (1995-06-01), Gurtler et al.
patent: 5426072 (1995-06-01), Finnila
patent: 5482873 (1996-01-01), Yang
patent: 5528080 (1996-06-01), Goldstein
patent: 5539227 (1996-07-01), Nakano
patent: 5539256 (1996-07-01), Mikagi
patent: 5587119 (1996-12-01), White
patent: 5596230 (1997-01-01), Hong
patent: 5599744 (1997-02-01), Koh et al.
patent: 5608237 (1997-03-01), Aizawa et al.
patent: 5614743 (1997-03-01), Mochizuki
patent: 5618752 (1997-04-01), Gaul
patent: 5635423 (1997-07-01), Huang et al.
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5646067 (1997-07-01), Gaul
patent: 5661344 (1997-08-01), Havemann et al.
patent: 5682062 (1997-10-01), Gaul
patent: 5698867 (1997-12-01), Bauer et al.
patent: 5699291 (1997-12-01), Tsunemine
patent: 5717247 (1998-02-01), Koh et al.
patent: 5750436 (1998-05-01), Yamaga et al.
patent: 5753529 (1998-05-01), Chang et al.
patent: 5767001 (1998-06-01), Bertagnolli et al.
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5811868 (1998-09-01), Bertin et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5827775 (1998-10-01), Miles et al.
patent: 5841197 (1998-11-01), Adamic, Jr.
patent: 5852320 (1998-12-01), Ichihashi
patent: 5858877 (1999-01-01), Dennison et al.
patent: 5869893 (1999-02-01), Koseki et al.
patent: 5930625 (1999-07-01), Lin et al.
patent: 5933758 (1999-08-01), Jain
patent: 5990562 (1999-11-01), Vallett
patent: 6001538 (1999-12-01), Chen et al.
patent: 6037244 (2000-03-01), Gardner et al.
patent: 6037248 (2000-03-01), Ahn
patent: 4-133472 (1992-05-01), None
V. Lehmann, “The Physics of Macropore Formation in Low Doped N-Type Silicon,”J. Electrochem. Soc., vol. 140, No. 10, Oct. 1993, pp. 2836-2843.
K.P. Muller et al., “Trench Storage Node Technology for Gigabit DRAM Generations,”Technical Digest of International Electron Devices Meeting, Dec. 8-11, 1996, pp. 507-510.
H. Horie et al., “Novel High Aspect Ratio Plug for Logic/DRAM LSIs Using Polysilicon-Aluminum Substitute (PAS),”Technical Digest of International Electron Devices Meeting, Dec. 8-11, 1996, pp. 946-948.
U.S. application No. 08/917,003, Ahn, filed Aug. 27, 1997.
U.S. application No. 08/917,443, Ahn, filed Aug. 22, 1997.
U.S. application No. 08/917,449, Geusic et al., filed Aug. 22, 1997.
U.S. application No. 09/095,774, Ahn, filed Jun. 10, 1998.
Low and High Dielectric Constant Thin Films for Integrated Circuit Applications, R.J. Gutmann, et al., Oct. 3-5, 1996, 6 pgs.
VLSI Multilevel Micro-Coaxial Interconnects for High Speed Devices, M.E. Thomas, I.A. Saadat & S. Sekigahama, IEEE 1990, pp. 90-55—90-58.
Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions, T. Ohba, T. Suzuki, T. Hara, Y. Furumura, & K. Wada, 1989 Materials Research Society, 9 pgs.
High Rate Low-Temperature Selective Tungsten, R.F. Foster, S. Tseng, L. Lane & K.Y. Ahn, 1988 Materials Research Society, 4 pgs.
Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature, T. Ohba, Y. Ohyama, S. Inoue, & M. Maeda, 1987 Materials Research Society, 8 pgs.
Sekine, M., “A New High-Density Plasma Etching System Using A Dipole-Ring Magnet,”Jpn. J. Appl. Phys., Nov. 1995, Pt. 1, No. 11.
“Polymers for high performance interconnects”
Ahn Kie Y.
Forbes Leonard
Geusic Joseph E.
Fahmy Wael
Micro)n Technology, Inc.
Potter Roy
Wells, St. John, Roberts Gregory & Matkin P.S.
LandOfFree
Coaxial integrated circuitry interconnect lines, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Coaxial integrated circuitry interconnect lines, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coaxial integrated circuitry interconnect lines, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2587805