Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2007-10-23
2007-10-23
Everhart, Caridad M. (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C257SE21128, C257S618000, C118S732000
Reexamination Certificate
active
11283272
ABSTRACT:
A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm3, a pore diameter of less than 0.1 mm and an internal surface area of the pores which is greater than 10,000 cm2/cm3. Semiconductor wafers having front surface coated by chemical vapor deposition (CVD) and a polished or etched back surface, prepared using the gas-permeable susceptor, have a nanotopography of the back surface, expressed as the PV (=peak to valley) height fluctuation, of less than 5 nm, and at the same time the halo of the back surface, expressed as haze, is less than 5 ppm.
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Patent Abstract of Japan corresponding to JP 60-254610.
Schauer Reinhard
Werner Norbert
Brooks & Kushman P.C.
Everhart Caridad M.
Silitronic AG
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