Coarsely controlling memory power states

Details Coarsely controlling memory power states Coarsely controlling memory power states

2011-06-07

2011-06-07

Cao, Chun (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S323000, C713S324000

Reexamination Certificate

active

07958380

ABSTRACT:
In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.

REFERENCES:
patent: 5835435 (1998-11-01), Bogin et al.
patent: 6877076 (2005-04-01), Cho et al.
patent: 7523282 (2009-04-01), Kapil et al.
patent: 2004/0260957 (2004-12-01), Jeddeloh et al.
patent: 2005/0125703 (2005-06-01), Lefurgy et al.
patent: 2006/0023482 (2006-02-01), Dreps et al.
CST Publications, “What is a 4-Rank DIMM Memory?” Feb. 3, 2006, pp. 1-4.

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