Coarse-grained look-up table architecture

Details Coarse-grained look-up table architecture Coarse-grained look-up table architecture

1995-06-07

1998-09-29

Bowler, Alyssa H.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 38, 326 39, 326 41, H03K 19177

Patent

active

058157263

ABSTRACT:
A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), and half- (330) and partially populated (320) multiplexer regions. The LAB includes two levels of function blocks. In a first level, there are eight four-input function blocks (601). In a second level, there are two four-input function blocks (670) and four secondary two-input function blocks (672). In one embodiment, these function blocks are implemented using look-up tables (LUTs). The LAB has combinatorial and registered outputs. The LAB also contains storage blocks (691) for implementing sequential or registered logic functions. The LAB has a carry chain for implementing logic functions requiring carry bits. The LAB may also be configured to implement a random access memory.

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