Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1998-11-13
2001-02-06
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S666000
Reexamination Certificate
active
06184585
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a co-packaged field effect transistor (FET) and integrated circuit (IC) for a portable electronic device and, more particularly, to a co-packaged FET and IC such as for a switching power supply employing at least one FET, a Schottky diode, and an appropriate control circuit IC.
With reference to
FIG. 1
, it is known to use FET transistors in a forward switching power supply which, for example, is a buck power supply
10
. The power supply
10
is coupled to a source of input DC power, Vin, having positive and negative terminals. An input filter capacitor
12
is coupled across the positive and negative terminals of Vin to provide a source of local energy storage.
First and second switching transistors Q
1
, Q
2
are coupled in series across the positive and negative terminals of Vin. It is known that transistors Q
1
and Q
2
may be MOS gated FETs, each having a respective gate, drain, and source terminal. As is known in the art, a control IC
16
supplies gating signals to the gate terminals G
1
, G
2
of transistors Q
1
and Q
2
, respectively, to produce a pulse with modulated (PWM) signal at the junctions of transistors Q
1
, Q
2
.
A Schottky diode D
1
is coupled in an anti-parallel configuration with transistor Q
2
in order to provide a free-wheeling current path in a shunt across the transistor, as is known in the art.
In order to provide a relatively steady and smooth supply of DC output power at Vo, a second order filter is provided which utilizes a series coupled inductor L and a shunt coupled capacitor
14
, as is also known in the art. The second order filter attenuates substantially all of the high frequency components of the PWM signal to produce the DC output voltage across the positive and negative terminals of Vo.
A sensing resistor Rs is provided in series with the inductor L so that a voltage may be developed across the resistor which is indicative of the current flowing through the inductor L. The sensed voltage is input to the control IC
16
so that the switching transistors Q
1
, Q
2
may be properly controlled, for example by current mode control. Further, a resistor divider is coupled from the positive terminal to the negative terminal of Vo and employs resistors R
1
and R
2
. A sensed voltage is taken from the junction of resistors R
1
and R
2
and is input to the control IC
16
. The sensed voltage provides information as to the voltage level at Vo and is also used by the control IC
16
to properly bias transistors Q
1
and Q
2
, for example by voltage mode control.
Because the switching frequency of transistors Q
1
and Q
2
may be relatively high and the current levels flowing through the transistors may also be relatively high, packaging considerations become critical. For example, transistors Q
1
and Q
2
, as well as diode D
1
, may operate at elevated temperatures due to the high switching frequencies and high current conditions. Further, the lengths of the interconnections between the transistors Q
1
and Q
2
, the control IC
16
, and diode D
1
may produce undesired stray inductances which cause excessive noise, excessive heat dissipation and spurious circuit operation.
Additionally, when the switching power supply
10
is incorporated into an electronic device which, for example, is a portable electronic device, the portion of the total circuit board area that is allocated to the power supply
10
becomes critical. Typically, power components such as transistors Q
1
, Q
2
and diode D
1
have relatively large footprints. TO-220 packages are often used to house transistors Q
1
and Q
2
, which are relatively large and have a relatively low silicon to footprint ratio (about 15%).
Consequently, the designers of portable electronic devices are under ever increasing pressure to reduce the amount of area and/or volume utilized by the power supply
10
.
Accordingly, a novel package for encapsulating power components and control circuitry to reduce the size and weight of the package, as well as to improve the circuit performance, by minimizing the parasitic inductances is needed in the art.
SUMMARY OF THE INVENTION
To overcome the disadvantages of the prior art, the present invention provides an electronic package for a portable electronic device which includes a power transistor die which has a lower surface and an upper surface, with the lower surface of the power transistor die mounted on the substrate, and a control circuit which controls the power transistor and is mounted to the upper surface of the power transistor die using an insulating epoxy.
In accordance with the invention, a semiconductor device includes a conductive lead frame having one or more pad areas. A first semiconductor die includes an MOS-gated semiconductor device which has opposing surfaces. A first opposing surface has at least one electrode that is disposed in electrical contact with the main pad area. A second one of the opposing surfaces has at least a gate electrode. A second semiconductor die includes a control IC with a first opposing surface that is disposed in contact with, but is electrically isolated from, the second opposing surface of the MOS-gated device. A second opposing surface of the control IC has at least one electrode that is electrically coupled to the gate electrode of the MOS-gated semiconductor device.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
REFERENCES:
patent: 4818895 (1989-04-01), Kaufman
patent: 4945445 (1990-07-01), Schmerda et al.
patent: 5008736 (1991-04-01), Davies et al.
patent: 5313095 (1994-05-01), Tagawa et al.
patent: 5798538 (1998-08-01), Nadd et al.
patent: 5894165 (1999-04-01), Ma et al.
patent: 5998856 (1999-12-01), Noda et al.
patent: 6057598 (2000-05-01), Payne et al.
patent: 6069401 (2000-05-01), Nakamura et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6077724 (2000-06-01), Chen
patent: 6107874 (2000-08-01), Ohashi
patent: 1231361 (1989-09-01), None
Cheah Chuan
Martinez Roberto
Clark Sheila V.
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
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