CMOS waveshaping buffer

Details CMOS waveshaping buffer CMOS waveshaping buffer

1998-07-24

2001-03-06

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S121000

Reexamination Certificate

active

06198306

ABSTRACT:

BACKGROUND
The proper operation of CMOS logic, such as buffer amplifiers, requires that the inputs settle to levels near the power supply rails (such as VDD and ground) and that transition between these levels occurs crisply. The realities of system design, however, frequently prevent this from occurring, because the signal levels are not always crisply rail-to-rail, because of high speed analog effects, noise, or other causes.
In the past, CMOS input level-shifters addressed this problem by cascading multiple stages to achieve high net voltage gain around the switch points. This reduced the probability that an internal logic device would be exposed to indeterminate logic states. This approach, however, presents a design trade off. With fewer stages of gain, indeterminate levels result in increased power dissipation and risk of operation faults, while more gain stages have a greater net delay in the signal propagation.
It is desirable to provide an improved CMOS logic level-shifter which produces precise switching, even for slowly changing input signals, and which does not require multiple gain stages to achieve the crisp switching transitions.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an improved CMOS buffer circuit.
It is another object of this invention to provide an improved CMOS waveshaping buffer, the output of which cannot remain in an ambiguous state.
It is an additional object of this invention to provide an improved CMOS buffer employing positive feedback to effect crisp signal transitions at the output.
It is a further object of this invention to provide an improved CMOS wave shaping buffer employing positive feedback from the output stage to the input stage whenever both stages are in their linear state to force crisp switching transitions of the output state.
In a preferred embodiment of the invention, a CMOS logic circuit has an input stage with a P-type MOS transistor and an N-type MOS transistor connected in series between first and second power supply rails, at different voltages. A source of input signals is connected in common to the gates of the input stage transistors. A CMOS output stage has a second P-type MOS transistor and a second N-type MOS transistor connected in series between the first and second power supply rails, with the gates of the output stage transistors coupled in common to the junction between the transistors of the input stage. The transistors of the input stage and the transistors of the output stage are then jointly connected to the positive and negative power supplies through a third P-type MOS transistor and a third N-type MOS transistor. This ensures precise signal switching of the transistors in the output stage, even for slowly changing signals supplied by the source of signals coupled to the gates of the transistors of the input stage.


REFERENCES:
patent: 3914702 (1975-10-01), Gehweiler
patent: 4532439 (1985-07-01), Koike
patent: 5012141 (1991-04-01), Tomisawa
patent: 5113150 (1992-05-01), Waizman
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5828235 (1998-10-01), Horiguchi et al.

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