CMOS tri-state buffer circuit and operation method thereof

Details CMOS tri-state buffer circuit and operation method thereof CMOS tri-state buffer circuit and operation method thereof

1993-07-23

1995-07-25

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326121, H03K 1900

Patent

active

054365775

ABSTRACT:
A 3-state buffer circuit applicable for a CMOS output drive circuit is disclosed. The output circuit provides reduced ground noise and delay time of an output signal by decreasing a counter-electromotive force generated upon turning ON of the output transistor. The circuit includes a subsidiary drive circuit for applying a voltage less than the power source Vcc to a gate of an NMOS transistor connected on the ground side of the drive circuit so that generation of the counter-electromotive force is minimized.

REFERENCES:
patent: 4638187 (1987-01-01), Boler
patent: 4827159 (1989-05-01), Naganuma
patent: 4985644 (1991-01-01), Okihara et al.
patent: 4985646 (1991-01-01), Kumagai
patent: 5059823 (1991-10-01), Ahsanullah
patent: 5206544 (1993-04-01), Chen et al.
patent: 5239211 (1993-08-01), Jinbo
patent: 5315173 (1994-05-01), Lee

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