CMOS transistor network to gate level model extractor for simula

Details CMOS transistor network to gate level model extractor for simula CMOS transistor network to gate level model extractor for simula

1995-03-17

1997-05-13

Trans, Vincent N.

Boots, shoes, and leggings

G06F 1750

Patent

active

056298587

ABSTRACT:
A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.

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