CMOS-TFT Array substrate and method for fabricating the same

Details CMOS-TFT Array substrate and method for fabricating the same CMOS-TFT Array substrate and method for fabricating the same

2006-07-04

2006-07-04

Geyer, Scott (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

Reexamination Certificate

active

07071036

ABSTRACT:
A TFT array substrate includes a substrate, first–third semiconductor layers, a gate insulating layer, a storage electrode, and a passivation layer. The gate insulating layer separates the first and second semiconductor layers and separates the second and third semiconductor layers. The storage electrode is positioned above the gate insulating layer. A passivation layer encloses the top and side surfaces of the storage electrode. The storage layer and source/drain regions of the first semiconductor layer are doped at the same time.

REFERENCES:
patent: 6140162 (2000-10-01), Yeo
patent: 6590229 (2003-07-01), Yamazaki et al.
patent: 2002/0068421 (2002-06-01), Yamazaki et al.
patent: 2004/0096999 (2004-05-01), Lin et al.
patent: 2004/0197967 (2004-10-01), Chen

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