CMOS tapered gate and synthesis method

Details CMOS tapered gate and synthesis method CMOS tapered gate and synthesis method

2005-11-15

2005-11-15

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06966046

ABSTRACT:
A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5168455 (1992-12-01), Hooper
patent: 5654898 (1997-08-01), Roetcisoender et al.
patent: 5724250 (1998-03-01), Kerzman et al.
patent: 6192508 (2001-02-01), Malik et al.
patent: 6397169 (2002-05-01), Shenoy et al.
patent: 2001/0049814 (2001-12-01), Matsumoto et al.
Hwang, W. et al., “Performance Analysis of Tapered Gate in PD/SOI CMOS Technology”, Proceedings of Technical Papers, 2001 International Symposium on VLSI Technology, Systema and Applications, Apr. 18-20, 2001, pp. 287-290.

Affiliated with

Also associated with

Rating

CMOS tapered gate and synthesis method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS tapered gate and synthesis method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS tapered gate and synthesis method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3519751