CMOS switch circuit for transferring high voltages, in...

Details CMOS switch circuit for transferring high voltages, in... CMOS switch circuit for transferring high voltages, in...

2000-06-02

2002-08-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S081000, C326S068000

Reexamination Certificate

active

06433583

ABSTRACT:

TECHNICAL FIELD
The present invention regards a CMOS switch circuit for transferring high voltages. In particular, the present invention refers to the final stage of the row or column decoder of a nonvolatile memory wherein cells are read at a higher voltage than the supply voltage (boosted read voltage).
BACKGROUND OF THE INVENTION
As is known, the need to have available nonvolatile memories with increasingly higher densities leads to the use of multilevel memories, where the information, stored in floating-gate regions of the cells, is coded through a number of logic levels, thus fractionating the quantity of charge stored in each cell.
FIG. 1
shows the characteristic that links the gate-to-source voltage Vgs to the drain-to-source current Ids of a flash cell for a two-level memory, i.e., wherein information is coded in each memory cell via a bit having two possible values, associated, respectively to an on condition of the cell and to an off condition of the cell, which in turn depends upon a programmed or not programmed state of the cell. In particular, in
FIG. 1
, Vtv and Vtw represent the value of the gate-to-source voltage Vgs at which a flash cell starts conducting current, in the case of a virgin (erased) cell and of a written cell, respectively. In a memory of this type, logic value “1” is generally associated to the characteristic having threshold voltage Vtv normally comprised between 0.5 and 2.5 V, and the logic value “0” is associated to the characteristic having threshold voltage Vtw generally higher than 5 V.
It is moreover known that reading a memory cell comprises converting the current absorbed by the memory cell, at a given gate-to-source voltage Vgs, into a voltage which is then translated to an output CMOS level.
In case of multilevel cells, the plane (Vgs, Ids) is divided by a number of characteristics (as shown, for example, in
FIG. 2
, which regards storing two bits per cell) corresponding to four logic values “11”, “10”, “01”, and “00”. In this case, the four logic values correspond to four different threshold values Vt
1
, Vt
2
, Vt
3
, and Vt
4
, which in turn are linked to different quantities of charge stored in the floating gate regions of the memory cells.
Cell programming is affected by uncertainty, and the characteristics both of FIG.
1
and of
FIG. 2
represent the central values of the actually obtainable distributions. In practice, each threshold value is associated to a respective distribution of values comprised between a minimum value and a maximum value set apart from the maximum value of the previous distribution and/or from the minimum value of the subsequent distribution in a way sufficient for enabling correct reading of the cells. In addition, each distribution may present a different amplitude, as shown, for example, in
FIG. 3
, which shows the distributions associated to memory cells, each storing two bits, and in which the scale is not uniform.
Also in this case, reading comprises converting the current flowing in a cell into a voltage. The thus obtained voltage is then compared with different voltage values that are intermediate between the threshold distributions referred to above.
One of the problems that arise when reading multilevel cells is linked to the read voltage applied to the gate terminals of the cells to be read. In fact, at the selected read voltage, all the read cells (with the possible exception of the cells programmed at the highest threshold value) must be on, so as to allow the converted voltage to be compared with the different voltage levels. Consequently, the read voltage must be at least higher than the last threshold voltage but one (Vt
3
in
FIG. 2
; VR in
FIG. 3
, here 6 V).
Such a high read voltage is particularly problematic to handle in devices that have a single supply voltage V
CC
, the nominal value of which is typically 3 V. In fact, high voltages are generated inside the nonvolatile memory by means of particular devices referred to as boosters or charge pumps. The Thevenin equivalent circuit of a charge pump
10
usable for this purpose is shown in FIG.
4
and comprises an ideal voltage source
11
generating a voltage V
1
and an equivalent resistor
12
connected in series to the ideal voltage source
11
. The equivalent resistor
12
is further connected to a load
13
represented as a current source.
FIG. 5
shows the output characteristic of the charge pump
10
. As may be noted, the output voltage V
0
of the charge pump
10
is maximum when load
13
does not absorb current, and reduces linearly as the current absorbed by the load
13
increases.
In particular, from
FIG. 5
it may be deduced that, when an output voltage not lower than V
p
is desired, the load
13
cannot absorb a current higher than I
pmax
. Usually, charge pumps integrated in CMOS technology manage to supply currents smaller than 1 mA. Word lines being read require 6 V, with a maximum ripple of 50 mV. For this reason, the output of the charge pump is connected to a voltage regulator which, being supplied by the voltage of the charge pump
10
, is able to yield a constant voltage of adequate value. It is evident that, in order to maintain the 6 V read voltage on the gate terminal of the cell to be read with adequate precision, it is necessary to consume as little current as possible during cell addressing.
The cell addressing phase, which determines switching of the row driving circuit, supplied at a 6-V read voltage, however, creates some problems. In fact, the switching control signals have a high logic level equal to the supply voltage, which, in the worst case, may be 2.5 V, so that there exists the problem of getting voltages with very different values to coexist in one and the same driving circuit, as will be explained in detail hereinafter.
The row decoder may be schematically represented by a number of inverters (one per row) controlled by a combinational circuit receiving the input addresses and having the function of driving the inverters in such a way that, each time, only one of them will have a high output. In particular, this combinational circuit sends a low logic signal to the inverter connected to the selected row (so that it will present a high output) and a high logic signal to all the other inverters. In this regard, see
FIG. 6
, showing one of the driving inverters
21
, comprising a pull-up PMOS transistor
22
and a pull-down NMOS transistor
23
, having coupled gate terminals (input node
24
), coupled drain terminals (output node
25
), and source terminals connected, respectively, to a first supply line
26
set at V
PP
and to a ground line.
The described simplified scheme works correctly when V
PP
=V
CC
, but does not work in the case described above, when the read voltage V
PP
is generated by a charge pump. In fact, in the latter case, the combinational circuit supplies, as a high logic level on input node
24
of the inverters of the non-selected rows, the read voltage V
CC
, whilst the first supply line
26
is set at the voltage V
PP
>V
CC
. In this situation, between the gate and the source terminals of the pull-up transistors
22
of the driving inverters
21
of the non-selected rows, there is a non-zero voltage drop. If this voltage reaches the value of the threshold voltage of the transistors
22
, the latter switches on, and the output node
25
of the inverters does not succeed in reaching a zero voltage value, as, instead, would be necessary to guarantee correctness of reading.
To solve the above problem, a first solution, shown in
FIG. 7
, involves the use of a positive feedback inverter using a feedback transistor
27
of PMOS type, connected between a first supply line
26
and the input node
24
of the driving inverter
21
, and having a gate terminal connected to the output node
25
.
FIG. 7
moreover shows a NAND gate
30
belonging to the row selection combinational circuit and supplied at the read voltage V
CC
via a second supply line
31
.
In this case, when the voltage on the output node
25
decreases, the feedback transistor
27
switches on

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