CMOS SRAM cell with PFET passgate devices

Details CMOS SRAM cell with PFET passgate devices CMOS SRAM cell with PFET passgate devices

2000-11-13

2002-01-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

06341083

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to CMOS Static Random Access Memory (SRAM) devices, and more particularly, to an SRAM cell having P channel field-effect transistors a s passgate devices to significantly reduce the surface area of all the transistors forming the cell, to improve the cell stability, and to lower the power dissipated by the cell.
BACKGROUND AND PRIOR ART
Conventional CMOS SRAM cells typically consist of six transistors: two P channel field effect transistors (PFETs) for a pull-up operation, two N channel field effect transistors (NFETs) for pull down, and two NFETs for input/output (i.e., passgate) access. As shown in
FIG. 1A
, P
1
and N
1
form an inverter which is cross-coupled with another inverter consisting of P
2
and N
2
. NL and NR are the passgate access devices which control reading from and writing into the cell. The corresponding layout for the above circuit is shown in FIG.
1
B. The two pull-up PFETs P
1
and P
2
are referenced by numeral
102
, the two pull down NFETs N
1
and N
2
by
111
, and the passgate NFETs NL and NR by
101
. For simplicity sake, metal shapes are not shown. In the particular layout, the word line (WL) is shown at first level metal M
1
along the X-direction. The bit lines and the GND line are represented at the second level metal M
2
along the Y-direction. Line
121
is the left bit line BL; line
122
, the right bit line BR; and line
120
, the vertical GND bus. The shape referenced by RX represents the active silicon area; PC, the polysilicon; CA, the contact from the first level metal M
1
to PC or RX; and NW, the region for the N-well of the P-channel devices.
A conventional SRAM array consists of m rows and n columns of the aforementioned SRAM cells. Cells of the same row share one WL, while cells of the same column share the same bit line pair, consisting of BL and BR. The aforementioned design is used in many SRAMs, including, e.g., 1 Mega-bit memory having, typically, 1024 by 1024 cells.
During standby, all the WLs are at low (i.e., at GND level) and all bit lines are biased to the standby voltage level (of the power supply) Vdd. Thus, the NFET passgate devices NL and NR of all the cells are shut off. A data bit
1
is maintained with P
1
and N
2
on, and P
2
and N
1
off, such that the left cell node CL is at high (i.e., Vdd) while CR is at low (GND). Correspondingly, a data bit
0
is maintained when P
2
and N
1
are on, and P
1
and N
2
off, which forces the right cell node CR to high (i.e., Vdd) and the left node CL to GND. During access time, one WL is selected by being switched on (to Vdd) such that half of the PFET passgate devices along the selected WL are turned on simultaneously. For each cell along the selected WL, one passgate device is turned on.
During a read access operation, either BL or BR are pulled down from their high (at Vdd) by the cell. BL is pulled down if the cell is at 0, whereas BR is pulled down if the cell is at 1. A bit select multiplexor then steers the selected bit pair(s) to appropriate sense amplifiers to generate the digital signals for the external circuitry requesting the read memory operation. The sense signals developed along the unselected bit columns are ignored. The cells along the selected WL that were not selected are referred to as the ‘half-selected’ cells.
During a write access operation, the bit select circuitry steers the input data into the selected bit pairs. To write a 1, BL is driven to high (i.e., to Vdd) and BR to low (i.e., to GND), shutting off N
1
and P
2
, while turning on N
2
and P
1
. To write a 0, BL is forced to low and BR to high. Along the unselected bit columns, BL and BR are coupled to Vdd and are gradually pulled down by the ‘half-selected’ cells, as previously described in the read operation. Thus, during a read access operation, all the cells along the selected WL are disturbed since one NFET passgate device of each SRAM cell remains on. During a write access, all the ‘half-selected’ cells are similarly disturbed as during the read operation. When a cell is at 0, the left cell node CL is at GND. When WL is raised to high (i.e., Vdd), the passgate device NL switches on, raising BL to Vdd and pulling the left cell node up. Thus, NL and N
1
act as a potential divider at CL between Vdd and GND. To prevent the node CL from rising beyond the threshold voltage of N
2
, the conductance of N
1
must be larger than the conductance of NL. Otherwise, N
2
turns on, pulling down the node CR, switching P
1
on, and raising the node CL from GND to Vdd. In such an instance, the cell is disturbed from its 0 state to a 1 state.
Thus, the ratio of the conductance of N
1
over the conductance of NL is a basic metric to measure the stability of the SRAM. This ratio is referred to by CMOS SRAM designers as ‘beta’ or ‘beta ratio’. It is defined as the ratio of the conductance of the pull down device
111
over the conductance of passgate device
101
.
There is no precise analytical expression for the conductance of the transistors. It is approximately proportional to m (pw/pl), wherein pl is the device channel length; pw, the device channel width and m, the effective carrier mobility. Accordingly, the beta of the cell can be approximated by the ratio of (m*pw/pl) of transistor N
1
and (m*pw/pl) of NL. If N
1
and NL have the same channel length, then the beta ratio becomes the ratio of the channel width of N
1
over the channel width of NL. Referring back to
FIG. 1B
, the channel width of N
1
is 0.36 &mgr;m, and the channel width of NL, 0.18 &mgr;m. Thus, the beta ratio equals 2. Depending on the SRAM application, beta ranges from 1.8 to 3. In general, beta needs to be bigger for faster operations.
Referring back to
FIG. 1A
, the six-transistor (6-T) cell shown therein has typically been the basic structure used in SRAM circuit designs, even though it is much larger than, e.g., a 1-T DRAM. Indeed, the cell size ratio between SRAM and DRAM generally exceeds 8. Many attempts have been made in the past to reduce the size of the SRAM cell. However, these attempts are routinely achieved by trade-offs between certain desirable feature characteristics of the 6-T SRAM cell. By way of example, in an article entitled “A 2.9 &mgr;m2 Embedded SRAM Cell with Co-salicide Direct-Strap Technology for 0.18 &mgr;m High Performance CMOS Logic”, published in IEDM 97, pp 847-850, the cell size is reduced by removing the pull-up P channel FETs. This replacement introduces significant problems when the cell stability degrades and standby power dissipation increases. A cell read operation becomes destructive, and write back provisions must be introduced. As a result, the cycle time increases significantly and the access power becomes unacceptably large. Further, a standby pull-up current must also be provided to retain the cell data. Thus, the standby power becomes very significant.
In a second example, in U.S. Pat. No. 5,747,979, “High Density SRAM Circuit”, issued Sep. 10, 1991, the pull-down NFET device is reduced to the same minimum size of the passgate device, without changing the NFET passgate device to a PFET passgate device. The area saving approaches those of the present invention. However, this reduction is attained at the expense of the cell beta degrading from 2 to 1. Thus, an array write back must be provided after every access, and no bit selection is possible. The cycle time needs to be stretched out and a considerable amount of extra power must be provided. Finally, the cells are still susceptible to disturbs, wherein the cells may have already flipped over before the sense signal is established for the subsequent write back. To minimize disturbing the less stable cells, data write back is provided after each access operation, as was required in the previous reference In another reference, U.S. Pat. No. 6,044,010, “Five Device SRAM Cell”, issued Mar. 28, 2000, the cell size is reduced by removing one of the two passgate transfer devices. By doing so, the read operation is slowed down for lack of bit pair sensing. Writing is also difficult

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