CMOS small signal switchable, impedence and voltage...

Details CMOS small signal switchable, impedence and voltage... CMOS small signal switchable, impedence and voltage...

2000-05-30

2001-10-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S026000

Reexamination Certificate

active

06310490

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to terminators which are applicable to metal oxide semiconductor on insulator (MOS-soi) with triple wells integrated circuit technology and which are particularly useful for terminator networks.
This related application(s) and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, N.Y.
The descriptions set forth in these co-pending applications are hereby incorporated into the present application by this reference.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled “Active termination circuit for computer interface use”, granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM's new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
It is therefore an object of the present invention to provide a terminator network adapted for MOS that can match the characteristic impedance of the line.
It is another object of the present invention to provide a terminator network which is fast and suitable for small signal swings and may also in a mixed technologies communication.
A further object of the present invention to provide a terminator network which has low current flow and low power consumption.
Still another objective of the present invention to provide a terminator network that provides ESD protection at the input of an attached circuit.
It is also an objective of the present invention to be able to switch into high impedance so that the driver can take control of the line and drive out for bi-directional data buses. Bi-directional data buses are used in all computer systems today.
It is still another objective of the present invention to be able to turnoff all currents to support the CMOS leakage test so that chips with defects can be found quickly and easily.
It is further an objective to be able to adjust the impedance of the terminator so that this circuit can have multiple usage.
It is another objective to be able to fine tune the terminator to have the desired reflection for the nets. This is to overcome any process tolerances.
It is also an objective of the present invention to be able to adjust the Vcenter voltage so that it can tune out any process mis-tracking of the pfet to nfets or mis-tracking of the power supplies from the sending to the receiving chip, and re-center the terminator voltage, so that maximum signal voltage can be obtain without creating skew between the zero and one logic levels.
A further object of the present invention to provide a terminator and receiver network which has low current flow and low power consumption.
It is also an objective to provide a receiver that can receive small signals properly. And have balanced noise tolerance between both logic levels.
Other objects and advantages of the invention will be apparent from the specification.
SUMMARY OF THE INVENTION
This invention provides a terminator and receiver network which is useful for fast transmission of digital data, eliminating or reducing overshoot and undershoot in signal transmission between chips and between systems, in serial links and data buses, for minimizing ringing and similar noise problems, for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) integrated circuit applications, and mixed vender technology interface communications. The demand for fast data transmission has pushed the data rate into hundreds of Mhz and Ghz and the preferred embodiment accommodates such speeds and reduces the signal swing so that the signal reach its desired digital ones or zeros voltage levels faster with lower power and with less noise generation.
The preferred embodiment of the invention control and adjustment of the impedance of the terminator so that it can operate the part in different packages as well as in system tuning for perfect termination. This will allow a part to have multiple usage's. This provides a basis for cost saving on chips with part number reduction and a high volume ASIC OEM useful circuit.
The preferred embodiment of the invention control and adjustment of the center voltage of the terminator so that maximum signal can be received and it does not create skew between the zero and one logic levels In case of mixed signal interfaces.
The receiver of the preferred embodiment provides good control on its threshold voltage to deal with small signals. It sets up a well balanced threshold voltage between the incoming logic levels, so that maximum noise tolerance between logic levels can be achieved for this receiver and the digital system.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.


REFERENCES:
patent: 4228369 (1980-10-01), Anantha et al.
patent: 4525830 (1985-07-01), Cohen et al.
patent: 4748426 (1988-05-01), Stewart
patent: 4989202 (1991-01-01), Soto et al.
patent: 5204860 (1993-04-01), Sparks
patent: 5387131 (1995-02-01), Foreman et al.
patent: 5493657 (1996-02-01), Van Brunt et al.
patent: 5523704 (1996-06-01), So
patent: 5675580 (1997-10-01), Lyon et al.
patent: 5729824 (1998-03-01), O'Neill et al.
patent: 5781028 (1998-07-01), Decuir
patent: 5850387 (1998-12-01), Lyon et al.
patent: 5917827 (1999-06-01), Cantwell
patent: 5977797 (1999-11-01), Gasparik
patent: 404020120A (1992-01-01), None

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