CMOS skewed static logic and method of synthesis

Details CMOS skewed static logic and method of synthesis CMOS skewed static logic and method of synthesis

2002-05-08

2003-09-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S104000, C326S106000

Reexamination Certificate

active

06624665

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is CMOS logic. The invention finds particular use in CMOS microprocessor circuits.
BACKGROUND OF THE INVENTION
CMOS logic gates are fundamental components of microprocessor circuits. Much effort is still placed in the design of logic gate families. Static CMOS logic gates offer simple cascading, but exhibit slow response. Dynamic logic gates that have precharge and evaluation operations controlled by a clock signal often cannot be cascaded directly. A dynamic gate output precharged to either a high or low logic level can cause improper charge operation of its next stage dynamic gate, leading to an erroneous evaluation result. If logic evaluation is through NMOS transistors of a gate, inputs for that gate should be precharged to a low logic level “L” to prevent unintended discharge. If PMOS, then precharge should be the high logic level “H” to prevent unintended charge up. If the input logic level is “X” during precharge and the output is denoted “Y”, gates may only be cascaded if Y(i)=X(j), where i<j and i, j denote the cascaded stage numbers.
Domino logic has been the logic family of choice for high-speed circuits in state-of-the-art processors such as Pentium Pro and Alpha. Domino logic circuits overcome the intrinsically slow nature of conventional static CMOS circuits, which is caused by the need for each gate to drive both NMOS and PMOS transistors. Domino logic circuits drive only NMOS transistors, thereby offering faster speed and smaller area compared to conventional static CMOS circuits.
Domino logic circuits have an inherently non-inverting nature, require strict timing constraints, and have a charge sharing problem. Domino logic with inverting and non-inverting outputs has been devised, but have their own set of problems.
NORA (NO RAce) circuits generate inverting logic only through strict cascading of NMOS and PMOS dynamic gates. Dual-rail logic circuits provide both inverting and non-inverting outputs, but occupy about twice the area of a standard domino gate. The extra power consumption of the dual-rail logic gates is also a serious drawback.
Some of these problems were addressed by Yee and Sechen, “Clock-Delayed Domino for Adder and Combinational Logic Design,” IEEE (Pub. No. 1063-6404/96)(1996). Clock-delayed domino (CD domino) eliminates the fundamental monotonic signal requirement by propagating a clock signal with controlled delay in parallel to the logic. However, the clock delay scheme is difficult to implement in practice. The clock delay must be large enough to allow evaluation of the slowest gates. Controlling this delay while satisfying the conflicting need for high-speed logic is a difficult task. The delay is set equal to the worst case pull-down delay of the corresponding dynamic gate, with an added margin for differences in signal delay, coupling parasistics, and fabrication process variations. Minimizing the set delay is thus difficult.
CD domino is also sensitive to process variations. In addition, it requires additional circuitry that takes up area and consumes power. Specifically, extra precharge transistors and a keeper PMOS transistor are used to reduce the effects of charge sharing, noise and coupling parasitics. Each CD domino gate typically requires a clock-delay logic device.
MS (monotonic static) CMOS has a dynamic evaluation path that can consist of either parallel-connected transistors or serially connected transistors. MS CMOS has both low-skewed and high-skewed NAND and NOR gates. A low skewed NAND gate is shown in FIG.
1
(
a
), a high skewed NAND gate in FIG.
1
(
b
), a low skewed NOR gate in FIG.
1
(
c
), and a high skewed NOR gate in FIG.
11
(
d
). The trip point of low skewed gates is lower than Vdd/2. The trip point of high skewed gates is higher than Vdd/2. In application of MS CMOS, high fan-in and high skewed gates are preferred for high-speed evaluation operation. Due to the parallel evaluation of low skewed NOR and high skewed NAND, their activity increases exponentially compared to serial evaluation type gates. An activity ration may be defined in terms of the number of inputs as:
Activity
⁢
 
⁢
Ratio
=
α
⁡
(
EP
)
α
⁡
(
ES
)
=
2
n
-
1
where, &agr; is the activity, EP is the number of parallel evaluations and ES is the number of serial evaluations.
FIG. 2
plots (in a solid line) the activity ratio, which increases drastically with the number of inputs due to the parallel evaluation.
FIG. 2
reveals that an 8-input low skewed NOR gate or high skewed NAND gate, both parallel evaluation gates, transits 255 times more than corresponding serial evaluation gates. Dynamic power consumption increases dramatically in proportion to &agr;.
MS CMOS also has significant static power consumption due to the parallel evaluation transistors. Leakage current in parallel-connected transistors with low threshold voltage causes large static power consumption in very deep submicron (VDSM) technology.
SUMMARY OF THE INVENTION
In the present invention, a CMOS gate is constructed with a logic function circuit and a positive feedback circuit. The positive feedback circuit, connected to an output of the logic function circuit, provides acceleration to the evaluation performed by logic function circuit. A trip point of the logic function circuit is deviated from Vdd/2 to provide fast transition.
A separate feature of the invention relates to the formation of large integrated circuits using the CMOS gates of the invention. Preferred circuits formed from CMOS gates of the invention implement a dual threshold voltage transistor (dual V
t
) configuration of the invention. The dual V
t
aspect of the invention is applied according to the topology of transistors used in a given evaluation path. Low V
t
devices are only used for transistors in stacked transistor portions of evaluation paths. More stacked transistors can be used by application of the CMOS gates of a preferred embodiment of the invention, since the preferred embodiment for a NAND gate and a NOR gate receive a precharging clock signal (Clk) or an inverted clock signal (Clk
−1
) to precharge output and internal feedback nodes of the NAND/NOR gates.


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