Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-18
2004-08-31
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S098000, C326S119000
Reexamination Certificate
active
06784694
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention is CMOS sequential logic. The invention finds particular use in CMOS microprocessor, ASIC, and DSP circuits.
BACKGROUND OF THE INVENTION
A flip-flop is an electronic circuit that stores a logical state of one or more data input signals in response to a clock pulse. Flip-flops are often used in computational circuits to operate in selected sequences during recurring clock intervals to receive and maintain data for a limited time period sufficient for other circuits within a system to further process data. At each rising or falling edge of a clock signal, data are stored in a set of flip-flops whose outputs are available to be applied as inputs to other combinatorial or sequential circuitry. Such flip-flops that store data on both the leading edge and the trailing edge of a clock pulse are referred to as double-edge triggered flip-flops.
In many very large scale integrated (VLSI) chips, the engineering design trend is to increase the pipeline stages for high throughput, which increases the number of flip-flops on a chip. This causes problems, though, because the power dissipation of the clocking system, including a clock distribution network and flip-flops is often the largest portion of total chip power consumption in VLSI chips due to the activity ratio of the clock signal being unity, and a significant increase in the interconnect line of clock trees.
In an ongoing desire to reduce power consumption in clock distribution networks, several small-swing clocking schemes have been proposed. Small-swing clocking schemes, however, have inherent disadvantages to designers since they require additional chip area during design. Additionally, four clock signals are required which can cause skew problems among the four clock signals. Furthermore, a reduced clock-swing clocking scheme requires an additional high substrate bias voltage to reduce the leakage current of the VLSI chip.
Other flip-flop designs such as a hybrid-latch flip-flop and a semi-dynamic flip-flop have also been proposed. These flip-flops operate faster than small-swing clocking schemed flip-flops, but also consume large amounts of power due to redundant transitions at internal nodes. Efforts to reduce the redundant power consumption and internal nodes of such flip-flops have led to the proposal of another type of flip-flop called the conditional capture flip-flop. Unfortunately, similar to the hybrid-latch flip-flop and the semi-dynamic flip-flop, the conditional capture flip-flop has a drawback of high power consumption in the clock tree since full-swing clock signals are required during operation.
SUMMARY OF THE INVENTION
A CMOS flip-flop circuit having a data-sampling front end and a data-transferring back end is provided by this invention. The front and back ends of the circuit are connected to one another between internal nodes charged and discharged according to an input data signal. The input data signal feeds a gate of an NMOS transistor as well as a gate of an PMOS transistor. Feeding a data input in this manner causes the internal nodes of the circuit to switch only when the input data signal changes, and not according to a clock signal inputted to the data-sampling front end. The flip-flop circuit further includes latches that prevent the internal nodes from having a floating voltage state, which reduces malfunction of the circuit.
In accordance with another aspect of the present invention, a new CMOS dynamic logic configuration for an edge triggered flip-flop includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a plurality of separate gate inputs and provide an output based on an input signal fed to a pair of transistor gates. A clock signal feeds a plurality of low threshold voltage NMOS transistors to trigger the flip-flop. Outputs from the pair of transistor gates define a first node and a second node, which have internal voltages. A first latch connected to the first node and a second latch connected to the second node have respective reference voltage sources to prevent a floating voltage state for each of the first and second nodes, and reduce power consumption during operation of the flip-flop.
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Kang Sung-Mo
Kim Chulwoo
Greer Burns & Crain Ltd.
The Board of Trustees of the University of Illinois
Tran Anh Q.
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