CMOS sensor camera with on-chip image compression

Details CMOS sensor camera with on-chip image compression CMOS sensor camera with on-chip image compression

1998-05-05

2002-07-09

Garber, Wendy R. (Department: 2712)

Television

Camera, system and detail

Solid-state image sensor

C348S312000

Reexamination Certificate

active

06417882

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to image acquisition and processing, and more specifically, to a method and apparatus operable to acquire an image as well as to perform image compression tasks.
BACKGROUND OF THE INVENTION
Today, digital image acquisition has two approaches. The first, based on charge coupled device (CCD) sensors, dominates the consumer market. The second approach is based on CMOS photoreceptor sensors.
The process used to fabricate CCD sensors limits their integration with clock drivers, A/D converters, or image processing circuits. As a result, multiple chips are required to complete systems that use CCD sensors.
On the other hand, the CMOS sensor technology enables integrated circuits to be built that contain the sensor array as well as circuitry for analog-to-digital conversion, image processing, and other still and video image processing.
Often, digitized images are compressed in order to store the data or to transmit the data over a telecommunications channel. There is a considerable amount of redundancy in a typical image, and often lossy compression, which suppresses some of the less noticeable components of the image, is used. In a typical image acquisition system, a CCD camera is followed by an A/D converter and then an expensive compression chip compresses the data. Compression may also be necessary to meet bandwidth requirements of a computer system.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of using a CMOS sensor array to perform a spatial to frequency transform of analog output signals from sensor elements of the array. With a CMOS sensor array, a set of wordlines and bitlines allows random access as with an SRAM.
With conventional systems based on CMOS sensor arrays, only one wordline and one set of bitlines of the CMOS sensor array is active at any given time. Using other system components, the signal on the bitline corresponding to the selected sensor element is amplified and converted to the digital domain. To convert the sensor output to the frequency domain, the output of a block (typically 8×8) of sensor elements must be multiplied by coefficients corresponding to a compression basis function and summed.
In the method of the present invention, the CMOS sensor array is read by activating wordlines and bitlines simultaneously. Pulse width modulation of the activation signals is used to impress coefficients along wordlines and bitlines. Current contributions are summed at the output of the array, thereby deriving an analog representation of a frequency domain value.
More specifically, to implement the method, the wordline activation period is divided into intervals, such that each interval has an accumulated pulsewidth whose proportion of the total period corresponds to a coefficient of the basis function. The bitline period activation period is divided into the same intervals, and each interval is further divided into subintervals, such that each subinterval has an accumulated pulsewidth whose proportion of the total period corresponds to a coefficient of the basis function. The result is the availability of pulsewidth modulated wordline and bitline signals.
In operation, a pulse is applied to at least one wordline and pulses are applied to at least one bitline. For any sensor element, its net current is determined by the coincidence of “on” times of its wordline and bitline. The number of wordlines and bitlines that can be simultaneously activated is related to the extent to which the matrix representing the coefficients of the basis function can be arranged such that rows and/or columns contain the same coefficient. Sensor outputs are obtained by activating wordlines and bitlines until the entire array is represented by its frequency components.
An additional feature of the invention is that the outputs of the sensor array may be compared to threshold values and only nonzero values converted to digital form. This conditional digitization can be performed “on-chip” and combined with quantization. Additional on-chip circuitry can be provided to perform run length or variable length encoding.
An advantage of the invention is that image sensing and image processing can be integrated—a single integrated circuit can perform both image acquisition and compression tasks. The analog transform is inherent in the readout of the sensor element outputs, and permits the digitization of only nonzero frequency components of the image. The result is a significant reduction in power requirements, as compared to transform devices that perform analog to digital conversion prior to the transform.


REFERENCES:
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patent: 5886659 (1999-03-01), Pain et al.
patent: 5920274 (1999-07-01), Gowda et al.
patent: 6067113 (2000-05-01), Hurwitz
patent: 6133954 (2000-10-01), Jie et al.

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