CMOS sense structure having silicon dioxide outer ring...

Details CMOS sense structure having silicon dioxide outer ring... CMOS sense structure having silicon dioxide outer ring...

2000-04-27

2001-10-23

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S547000, C257S181000, C257S355000

Reexamination Certificate

active

06307239

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89107355, filed Apr. 19, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a CMOS sense structure. More particularly, the present invention relates to a CMOS sense structure having a silicon dioxide outer ring around the sense region for lowering surface leakage and edge junction leakage.
2. Description of Related Art
FIG. 1
is a schematic cross-sectional side view of a conventional CMOS sense structure. As shown in
FIG. 1
, the CMOS sense structure includes a substrate
10
, a n
+
region
12
, a n
−
region
14
, isolation regions
16
and field implant regions
18
. The substrate
10
can be a P-type substrate (or a P-well), for example. The n
+
region
12
and the n
−
region
14
are formed by implanting identical ions, but with different concentrations, into the substrate
10
. The concentration of ions inside the n
+
region is higher than the concentration of ions inside the n
−
region. The n
+
region
12
and the n
−
region
14
together form the diode in the sense region. The isolation region
16
and the field implant region
18
on each side of the sense region are used for isolating device regions (not shown in the figure).
Because etching is conducted in the process of forming spacers or polysilicon gates in the device regions, the depletion region
22
near the edge of the sense region may be etched, leading to surface damages. Consequently, a large dark current may form on the surface of the sense region. The dark current is referred to as surface leakage. An excessive surface leak may result in poor image quality.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a CMOS sense structure having an outer silicon dioxide ring around the sense region. The outer silicon dioxide ring serves as a protective layer to prevent any damages on the depletion region near the edge of the sense region when spacer etching or polysilicon etching is conducted to reduce the leakage current.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure includes a substrate, a n
−
region, a n
+
region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n
−
region is formed in the substrate, and the n
+
region is formed within the n
−
region. The isolation region is formed in the substrate next to the edge of the n
−
region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n
−
region, a portion of the isolation region and a portion of the n
+
region.
The substrate can be a P-type substrate. The n
+
region and the n
−
region form a diode structure. The isolation region is formed using a silicon dioxide. The field implant region is formed by implanting p-type ions. In addition, the silicon dioxide outer ring is formed over the n
−
region, a portion of the isolation region and a portion of the n
+
region. Hence, the outer ring can protect the depletion region of the sense region against any damages that are caused by etching and reducing the current leak.
The invention also provides a method of forming a CMOS sense structure having a silicon dioxide outer ring around the sense region. First, a substrate having a device region, a plurality of isolation regions and a CMOS sense region is provided. One side of the isolation region is in contact with the device region while the other side of the isolation region is in contact with the CMOS sense region. There is a field implant region under each isolation region. A silicon dioxide outer ring is formed over the isolation region and the edge junction of the CMOS sense region. Finally, an n
+
and an n
−
implant are conducted sequentially, implanting ions into the CMOS sense region.
The substrate can be a P-type substrate. The n
+
region and the n
−
region form a diode structure. The isolation region is formed using a silicon dioxide. The field implant region is formed by implanting p-type ions. In this invention, since the silicon dioxide outer ring is formed before the n
+
and n
−
implants, distance of separation between the n
+


−
/field implant regions is increased. Hence, edge junction leakage is lowered.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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patent: 4228448 (1980-10-01), Lalumia et al.
patent: 5648665 (1997-07-01), Terasawa
patent: 5841167 (1998-11-01), Grimaldi et al.
patent: 6066884 (2000-05-01), Krutsick
patent: 6111283 (2000-08-01), Yang et al.
patent: 6140694 (2000-10-01), Chen et al.
patent: 6150701 (2000-11-01), Lee
patent: 6191015 (2001-02-01), Losehand et al.
patent: 05129649 (1993-05-01), None

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