CMOS semiconductor integrated circuit

Details CMOS semiconductor integrated circuit CMOS semiconductor integrated circuit

2000-05-01

2001-10-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C327S534000

Reexamination Certificate

active

06310492

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a field effect transistor (FET).
Low power consumption in semiconductor integrated circuits has been required. Particularly, for the case of portable equipments that run on batteries, since their battery capacity is limited, there have been strong demands for reducing power consumption in semiconductor integrated circuits for use in such portable equipments.
U.S. Pat. No. 5,644,266 (issued Jul. 1, 1997) and PCT Publication No. WO97/32399 (published Sep. 4, 1997) each disclose a technique capable of causing the back gate electrode voltage of a MOS (metal oxide semiconductor) FET to vary for the purpose of controlling the threshold voltage of the FET. By virtue of these prior art techniques, it is possible to provide fast, low power consuming FETs.
Recently, in the field of CMOS (complementary metal oxide semiconductor)-type semiconductor integrated circuit, with the advance of ultra miniaturization process technology, it has become possible to employ a dual gate process in which P-type polysilicon is used as the gate electrode material for P-channel FETs and N-type polysilicon is used as the gate electrode material for N-channel FETs. P-type polysilicon is, for example, a boron (B) doped polysilicon which exhibits the nature of P-type semiconductor.
H. Ushizaka et al. reported, in their paper entitled “The Process Dependence on Positive Bias Temperature Aging Instability of p
+
(B) Polysilicon-Gate MOS Devices”, IEEE Transactions on Electron Devices, Vol. 40, No. 5, pp. 932-937, May 1993, that a P-channel FET with a P-type polysilicon gate electrode had undergone serious degradation in electrical characteristic due to the influence of thermal stress at the aging time. When thermal stress is placed onto a P-type polysilicon gate electrode with a positive bias voltage applied thereto, in such a gate electrode the bond of a boron ion (B
−
) and a hydrogen ion (H
+
) is disconnected and, as a result, the hydrogen ion having a plus electric charge travels to the interface between a gate dioxide layer (SiO
2
) and a silicon (Si) substrate due to the influence of an electric field by the bias voltage. Such a mechanism has been considered to cause characteristic degradation, e.g., the drop in the threshold voltage of a P-channel FET. Further, H. Ushizaka et al. reported that the characteristics of the P-channel FET were improved by N
2
gas annealing.
W. W. Abadeer et al. confirmed the validity of such N
2
gas annealing in their paper entitled “Long-Term Bias Temperature Reliability of P+ Polysilicon FET Devices”, IEEE Transactions on Electron Devices, Vol. 42, No. 2, pp. 360-362, February 1995.
Apart from the above, in a semiconductor integrated circuit in which an analog circuit portion and a digital circuit portion are mounted in a mixed fashion, there is a situation allowing the digital circuit portion to stop functioning while letting the analog circuit portion in operation. Under such a condition, if the power supply for the digital circuit portion is shut off to pull the output voltage of the power supply down to the zero level, this will reduce power consumption in the semiconductor integrated circuit to a considerable extent. However, the employment of a dual gate process produces some problems. Suppose, for example, that a source electrode of a P-channel FET in the digital circuit portion is connected to a power supply and that a back gate electrode of the P-channel FET is brought into direct connection with the aforesaid source electrode. In this case, when the power supply is shut off, the voltage of each of the source and back gate electrodes of the P-channel FET becomes the zero level. As a consequence, the P-channel FET enters a state of not functioning as a transistor. If, in such a state, positive voltage is continuously applied to the gate electrode of the P-channel FET from the analog circuit portion, this produces the problem that the P-channel FET undergoes degradation in electrical characteristic owing to the foregoing mechanism, therefore being unable to regain its original electrical characteristics. Even when the foregoing N
2
gas annealing is carried out in a step of the semiconductor integrated circuit fabrication, the same problem occurs.
In a differential amplifier, it is possible to achieve a reduction in power consumption by turning off a current source transistor for operating a pair of input transistors. However, when employing a dual gate process, the same problem as mentioned above arises for the reason that it is likely that, in a state in which the voltage of each of the source and back gate electrodes of a P-channel FET forming one of the input transistor pair becomes the zero level, positive Voltage is continuously applied to the gate electrode of the P-channel FET.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to protect a P-channel FET with a gate electrode of P-type semiconductor from degradation by the devising of a circuit configuration, in a semiconductor integrated circuit having a low power consumption mode.
In order to achieve the object, the present invention provides a semiconductor integrated circuit which employs the following configuration. More specifically, the semiconductor integrated circuit of the present invention comprises a P-channel FET which has a drain electrode, a source electrode, a gate electrode formed of a P-type semiconductor material, and a back gate electrode and which is configured such that in a normal operation mode (a) a certain voltage is supplied from a power supply to the source electrode and (b) another voltage representative of an input signal is supplied to the gate electrode, wherein the semiconductor integrated circuit further comprises control means, responsive to a control signal which is asserted when reducing power consumption in the semiconductor integrated circuit, for controlling at least one of the voltage of the gate electrode and the voltage of the back gate electrode so as to prevent the gate electrode voltage from exceeding the back gate electrode voltage, in order to protect the P-channel FET which is being in a state of not functioning as a transistor from degradation. As a result of the adoption of such a configuration, even when an ion of hydrogen having a plus electric charge is generated in the gate electrode due to the influence of thermal stress, the hydrogen ion will remain within the gate electrode, whereby the P-channel FET is prevented from undergoing characteristic degradation.
In accordance with one embodiment of the present invention, in a low power consumption mode in which the back gate electrode voltage of the P-channel FET becomes the ground voltage level (=0 V), the gate electrode voltage of the P-channel FET is fixed at the non-positive voltage level (for example, 0 V) in response to the control signal.
In accordance with another embodiment of the present invention, in response to the control signal, the back gate electrode voltage of the P-channel FET is fixed at a positive voltage not lower than the gate electrode voltage of the P-channel FET. It is to be noted that this embodiment of the present invention differs much from the foregoing prior art techniques (i.e., U.S. Pat. No. 5,644,266 and PCT Publication No. WO97/32399) in that the back gate electrode voltage of the P-channel FET in the state of not functioning as a transistor is subjected to control.
Further, in accordance with still another embodiment of the present invention, in response to the control signal, control is carried out so as not to produce any potential difference between the gate and back gate electrodes of the P-channel FET.


REFERENCES:
patent: 5004936 (1991-04-01), Andresen
patent: 5338978 (1994-08-01), Larsen et al.
patent: 5341034 (1994-08-01), Matthews
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5644266 (1997-07-01), Chen et al.
patent: 5844425 (1998-12-01), Nguyen et al.
patent: 5926056 (1999-07-01), Morris et al.
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