CMOS semiconductor device comprising graded junctions with reduc

Details CMOS semiconductor device comprising graded junctions with reduc CMOS semiconductor device comprising graded junctions with reduc

1997-09-05

1999-09-14

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257408, 257917, H01L 2978, H01L 21336

Patent

active

059526939

ABSTRACT:
A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

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Nayak, Deepak K., "A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/P nLDD Junctions for Deep-Submicron CMOS Logica Technology", IEEE Electron Device Letters, vol. 18, No. 6, 1997, pp. 281-283.

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