CMOS semiconductor device

Details CMOS semiconductor device CMOS semiconductor device

1997-01-14

2001-07-03

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S391000, C257S379000, C257S530000, C257S541000

Reexamination Certificate

active

06255700

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to lowering of the voltage of a power-supply semiconductor integrated circuit.
An existing voltage detector or voltage regulator comprising a CMOS transistor uses an N-type gate electrode for the gate electrode of an NMOS transistor of the CMOS transistor and an N-type gate electrode for the gate electrode of a PMOS transistor of the CMOS transistor.
FIG. 3
shows a circuit block diagram of a voltage detector. The voltage detector comprises a reference voltage circuit
301
; a voltage division circuit
302
, a voltage comparison circuit
303
, and an output circuit
304
. The reference voltage circuit
301
comprises a depletion-type NMOS transistor and an enhancement-type NMOS transistor which mutually connect in series between a power supply line
202
and a ground line
201
and has a function for outputting a constant voltage to the joint A
111
. The voltage division circuit
302
comprises a plurality of series resistances connected between the power supply line
202
and the ground line
201
and has a function for dividing a power supply voltage by using a joint B
112
as a separating point. The voltage comparison circuit
303
comprises PMOS transistors and NMOS transistors, which are connected between the power supply line
202
and the ground line
201
, connects with the reference voltage circuit
301
at the joint A
111
and with the voltage division circuit
302
at the joint B
112
, compares the voltage difference between the joint A
111
and the joint B
112
and has a function of outputting a voltage equal to a power supply voltage to a joint C
113
when the voltage at the joint B
112
is lower than the voltage at the joint A
111
.
The output circuit
304
comprises an inverter constituted by combining a PMOS transistor with an NMOS transistor, in which the source of the PMOS transistor connects with the power supply line
202
, the drain of the PMOS transistor connects with the drain of the NMOS transistor, and the source of the NMOS transistor connects with the ground line
201
.
The voltage comparison circuit
303
and the gate electrode of the inverter are connected to each other at the joint C
113
. When the output of the voltage comparison circuit
303
is received by the gate electrodes of the PMOS and NMOS transistors, the drain joint between the PMOS and NMOS transistors has a function of outputting a voltage equal to the power supply voltage.
A detection voltage is determined by the reference voltage which is outputted by the reference voltage circuit
301
and the ratio of the resistance of high-resistance polysilicon, and a desired output voltage can be obtained by a polysilicon fuse built. Moreover, high-resistance polysilicon with a high resistance value is used to decrease current consumption and the high-resistance polysilicon and a CMOS transistor are indispensable components for a CMOS power supply IC.
The voltage detector has a function for decreasing an output voltage to 0 V when the power supply voltage is equal to the detection voltage or lower (e.g. 0.8 V or lower).
FIG. 6
shows a circuit block diagram of the voltage regulator. The voltage regulator comprises a reference voltage circuit
311
, a voltage division circuit
312
, a voltage comparison circuit
313
, and an output circuit
314
. The reference voltage circuit
311
comprises a depletion-type NMOS transistor and an enhancement-type NMOS transistor which mutually connect in series between a power supply
212
and an earthing line
211
and has a function of a constant output voltage to the joint A
121
.
The voltage division circuit
312
comprises a plurality of series resistances connected between the power supply line
212
and the ground line
211
, and has a function of dividing a power supply voltage by using a joint B
122
as a separating point.
The voltage comparison circuit
313
comprises PMOS transistors and NMOS transistors, which are connected between the power supply line
212
and the ground line
211
, and connects with the reference voltage circuit
311
at the joint A
121
and with the voltage division circuit
312
at the joint B
122
, and compares the voltage difference between the joint A
121
and the joint B
122
and has a function of outputting the gate controlled voltage to the output circuit
314
.
The output circuit
314
comprises a PMOS transistor or an NMOS transistor. When the circuit
314
comprises the output PMOS transistor, it is constituted so as to connect the source with the power supply line
212
and the drain of the PMOS with a voltage division circuit
312
.
When the output circuit
314
comprises the NMOS transistor, it is constituted so as to connect the drain with the power supply line
212
and the source of the NMOS transistor with the voltage division circuit
312
.
Moreover, the output circuit
314
is constituted so as to connect the voltage comparison circuit
313
with the gate electrode of the PMOS or NMOS transistor at the joint C
123
and receive the output of the voltage comparison circuit
313
by the gate electrode of the PMOS or NMOS transistor, and has a function of outputting a voltage to an output terminal
133
connected to the drain of the PMOS transistor or the source of the NMOS transistor.
The voltage regulator has a function of continuously outputting a constant output voltage even if a power supply voltage or a load fluctuates.
FIG. 23
shows an existing reference voltage circuit used for a voltage detector or voltage regulator. The reference voltage circuit comprises a depletion-type NMOS transistor
401
and an enhancement type NMOS transistor
402
which mutually connect in series between a power supply line
222
and a ground line
221
and has a function of outputting a constant output voltage to the joint A
161
.
The depletion-type NMOS transistor
401
connects the gate with the source to equalize the potential with that of a substrate and connects the source with the drain of the enhancement-type NMOS transistor. The enhancement-type NMOS transistor
402
connects the gate with the drain to equalize the potential of the substrate with that of the source.
Moreover, the drain of the depletion-type NMOS transistor
401
connects with the power supply line
222
, the source of the enhancement-type NMOS transistor connects with the ground line
221
, and the joint A
161
between the depletion-type transistor
401
and the enhancement-type transistor
402
is used as an output terminal.
[0004]—Existing Example (Fabrication Method)
In general, an existing voltage detector and a voltage regulator comprising a CMOS transistor respectively are fabricated differently from each other by forming a high resistance and a gate electrode with a polysilicon film and changing the amount of impurities to be introduced into the polysilicon film.
An existing method for fabricating high-resistance polysilicon and a polysilicon-gate CMOS transistor on the same substrate is described below by taking a P substrate as an example and referring to
FIGS. 20
to
22
.
An N well
2
is first formed on a P-type silicon substrate
1
through ion implantation and thermal diffusion and thereafter, a P-type region
3
and an N-type region
4
are formed through ion implantation to separate devices. Then, a field oxide film
5
and a gate oxide film
6
are formed {FIG.
21
A} ions are implanted into a channel region for transistor threshold control {FIG.
2
B} and a polysilicon film
7
is deposited {FIG.
21
C}. Then, ions are implanted into high-resistance polysilicon
8
to control the resistance value {FIG.
21
D}, a CVD oxide film
9
wider than a portion serving as the high-resistance polysilicon
8
is deposited, the pre-deposition of phosphorus is performed, and high-concentration phosphorus is diffused in the polysilicon film {FIG.
21
E}. Then, the oxide film is removed from the polysilicon and thereafter the high-resistance polysilicon
8
is formed through etching {FIG.
21
F}. Polysi

Affiliated with

Also associated with

Rating

CMOS semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2530700