CMOS semiconductor device

Details CMOS semiconductor device CMOS semiconductor device

1998-05-04

2000-11-28

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257372, 257373, 257394, 257409, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

061539155

ABSTRACT:
In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

REFERENCES:
patent: 4035826 (1977-07-01), Morton et al.
patent: 4614959 (1986-09-01), Nakagawa
patent: 5274259 (1993-12-01), Grabowski et al.
patent: 5319236 (1994-06-01), Fujihira
patent: 5763926 (1998-06-01), Yamamoto et al.
IEEE Electron Device Letters, "Failure in CMOS Circuits Induced by Hot Carriers in Multi-Gate Transistors", vol. 9, No. 11, 1988, pp. 564-566.

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