CMOS semiconductor circuit for generating high output voltage

Electronic digital logic circuitry – Interface – Current driving

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Details

326 83, 326 86, 326112, H03K 19094, H03K 1920

Patent

active

060313951

ABSTRACT:
A semiconductor circuit for generating a high output voltage which includes: a first dividing circuit connected to a first fixed voltage and a second dividing circuit connected to second fixed voltage lower than the first fixed voltage, each dividing circuit having a plurality of stages for dividing an input voltage, a total number of the stages being sufficient to ensure that individual voltage drops across the stages, respectively, do not exceed a channel breakdown voltage for a predetermined transistor technology; a pull-up circuit, connected to the first dividing circuit, for pulling up an output voltage to a first predetermined level, the pull-up circuit having a plurality of modules sufficient in number to ensure that individual voltage changes across the modules, respectively, do not exceed the breakdown voltage; a pull-down circuit, connected to the second dividing circuit, for pulling down the output voltage to a second predetermined level, the pull-down circuit having a plurality of modules sufficient in number to ensure that individual voltage drops across the modules, respectively, do not exceed the breakdown voltage; a first control circuit for enabling or disabling operation of the pull-up circuit based upon at least one voltage from the first voltage dividing circuit; and a second control circuit for disabling or enabling the pull-down circuit, respective to the first control circuit, based upon at least one voltage from the second voltage dividing circuit.

REFERENCES:
patent: 5465054 (1995-11-01), Erhart
patent: 5604449 (1997-02-01), Erhart et al.
patent: 5729155 (1998-03-01), Kobatake
patent: 5748025 (1998-05-01), Ng et al.
patent: 5808480 (1998-09-01), Morris
patent: 5955891 (1999-09-01), Makino et al.

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