CMOS regenerative sense amplifier with high speed latching

Details CMOS regenerative sense amplifier with high speed latching CMOS regenerative sense amplifier with high speed latching

1990-04-03

1991-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 3072721, 307481, H03F 345, H03K 19094

Patent

active

050577182

ABSTRACT:
The present invention provides for a sense amplifier having a pair of input nodes connected through isolating PMOS transistors to the differential input terminals of the amplifier. Each of the input nodes is also connected to the gates of a pair of carefully matched NMOS transistors and to the drain of the other of the matched pair. In addition, each of the input nodes is connected to the gate of one of two drive NMOS transistors. The drains of the drive NMOS transistors are each connected to the gates of two output PMOS transistors, the drains of which form the output terminals of the sense amplifier. The sources of the matched NMOS transistor pair are coupled to ground by a NMOS transistor and the sources of the drive NMOS transistors are coupled to ground by another NMOS transistor. When the differential signals at the input terminals are to be sensed and latched, the sources of matched transistor pair and the sources of the drive transistors are sequentially connected to ground. Thus even though the input nodes of the amplifier are pulled toward ground in a high-speed operation, the input node at the higher voltage is still able to turn on its corresponding drive NMOS transistor. Latching of the sense amplifier proceeds safely.

REFERENCES:
patent: 4649301 (1987-03-01), Van Tran
patent: 4791324 (1988-12-01), Hodapp
patent: 4843264 (1989-06-01), Galbraith

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