CMOS RAM having a complementary channel sense amplifier

Details CMOS RAM having a complementary channel sense amplifier CMOS RAM having a complementary channel sense amplifier

1990-10-30

1991-10-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365190, 365203, G11C 700

Patent

active

050580736

ABSTRACT:
A semiconductor memory such as a dynamic RAM (Random Access Memory) implemented by complementary MOS (CMOS) transistors includes a plurality of bit line pairs each constituted by a first and a second complementary bit line for transferring data, and a plurality of word lines extending across the bit line pairs. A plurality of memory cells are located at the intersecting points of the bit line pairs and word lines and connected to the latter for storing data therein. A plurality of sense amplifier circuits are each associated with respect to one of the bit line pairs for sensing potentials on a first and a second node associated with the bit line pair and amplifying the sensed potentials. Each of the sense amplifier circuits includes a first and a second sense amplifier of opposite polarity. A plurality of first field effect transistors (FETs) each has a source-drain path for connecting to the first node the first bit line of respective one of the bit line pairs. A plurality of second FETs each has a source-drain path for connecting to the second node the second bit line of respective one of the bit line pairs. The plurality of first and second field effect transistors individually have commonly connected control electrodes to which a gate signal is applied. The plurality of first and second field effect transistors are complementarily controlled in response to the gate signal to transfer one of the potentials on the first and second bit lines to one of the first and second sense amplifiers.

REFERENCES:
patent: Re32682 (1988-05-01), Eaton et al.
patent: 4618947 (1986-10-01), Tran et al.
patent: 4710901 (1987-12-01), Kumanoya et al.
patent: 4829483 (1989-05-01), Ogihara
patent: 4931992 (1990-06-01), Ogihara et al.
IEEE 1985; "FAM 17.2: A 90ns 1Mb DRAM with Multi-Bit Test Mode"; pp. 240, 241, Masaki Kumanoya, Kazuyasu Fujishima, Katsuhiro Tsukamoto, Yasumasa Nishimura.

Affiliated with

Also associated with

Rating

CMOS RAM having a complementary channel sense amplifier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS RAM having a complementary channel sense amplifier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS RAM having a complementary channel sense amplifier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-996411