CMOS process

Details CMOS process CMOS process

2001-03-28

2002-12-10

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S391000, C257S392000, C257S402000

Reexamination Certificate

active

06492671

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to a CMOS process and more specifically to a method of producing a high-voltage MOS transistor in a CMOS process.
BACKGROUND OF THE INVENTION
In ADSL (Asymmetric Digital Subscriber Line) systems, data are transferred at high speed from a central office to subscribers on existing telephone lines.
In the central office, there is a separate ADSL line card having an analog front end comprising e.g. high-speed AD/DA converters, line drivers and receivers.
To achieve required performance concerning speed and signal-to-noise ratio, the line driver has to work with a supply voltage above 10V. At the same time, modern mixed signal technologies, using submicron channel length, have to be used for the AD/DA part. Such technologies can normally not operate above 5V. Therefore, the line driver is implemented on a separate chip using bipolar technology, while the remaining part of the analog front end is implemented in an ordinary CMOS technology suited for modem AD/DA-design.
If extra process steps were added to the standard CMOS process, it would of course be possible to include the line driver on the same chip as the rest of Me analog front end, but such a process would be more complicated and more expensive compared to the standard technology. It could e.g. be done using a BiCMOS process, i.e. a process including both bipolar and CMOS transistors, where the bipolar pan is optimized for the line driver. However, as mentioned above, such a process is more expensive and complicated compared to a single CMOS process.
It could also be implemented using a dual gate CMOS process, which includes CMOS devices with two different gate oxides. A thicker gate oxide will then be able to handle the higher voltage. Such a process will of course also be more complicated Furthermore, it will be hard to obtain the necessary performances for ADSL using such types of MOS devices because a thicker gate oxide decreases the performance at high frequency.
A further way would be to add an LDMOS device to the process, where the channel length and the threshold voltage are set by adding an extra p-doped region inside the n-well. Extra process steps are then needed and the low-voltage devices and the high-voltage device will get different threshold voltages.
BRIEF DESCRIPTION OF THE INVENTION
The object of the invention is to implement all necessary functions for the analog front end on the same chip, i.e. including also the line drivers, by using an ordinary CMOS process flow suited for low voltage mixed signal design.
This is attained in that the design of the MOS transistor is modified in such a way that the process includes high-voltage MOS transistors with similar frequency performance and with the same threshold voltage as the low voltage n-channel MOS transistor. The high voltage MOS transistor is added without any extra mask steps or other steps to the process flow. Instead, the voltage is distributed inside an extended field region consisting of the same n-well dopants as is formed for the low-voltage PMOS transistor.
Hereby, in the same CMOS process, a high-voltage MOS transistor will be produced together with a low-voltage NMOS transistor and a low-voltage PMOS transistor on the same substrate. Further, the supply voltage for the low-voltage transistors can then be decreased without changing the breakdown voltage capability for the high voltage transistor.
BRIEF DESCRIPTION OF THE DRAWING
The invention will be described more in detail with reference to the appended drawing on which
FIGS. 1-12
illustrate different steps in a CMOS process according to the invention.


REFERENCES:
patent: 4628341 (1986-12-01), Thomas
patent: 4701796 (1987-10-01), Kamiya
S. Wolf, “Silicon Processing for the VLSI Era, vol. 2 -Process Integration”, ISBN 0-961672-4-5, Lattice Press California 1990, pp. 17-44.

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