CMOS pixel with dual gate PMOS

Details CMOS pixel with dual gate PMOS CMOS pixel with dual gate PMOS

2005-03-22

2005-03-22

Le, Dung (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S261000, C257S262000

Reexamination Certificate

active

06870209

ABSTRACT:
A pixel circuit with a dual gate PMOS is formed by forming two P+regions in an N−well. The N−well is in a P−type substrate. The two P+regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N−well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N−well potential so that they remain reverse biased with respect to the N−well. One of the P+regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N−well forms a second gate for the dual gate PMOS transistor since the potential of the N−well12affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N−well.

REFERENCES:
patent: 5917547 (1999-06-01), Merrill et al.
patent: 5923369 (1999-07-01), Merrill et al.
patent: 5952686 (1999-09-01), Chou et al.
patent: 6127697 (2000-10-01), Guidash
patent: 6147362 (2000-11-01), Keyser
patent: 20010011736 (2001-08-01), Dierickx

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