CMOS-PECL level conversion circuit

Details CMOS-PECL level conversion circuit CMOS-PECL level conversion circuit

1996-01-05

1997-03-25

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 33, 326 68, 326115, H03K 19003

Patent

active

056148437

ABSTRACT:
A level conversion circuit is provided which can obtain a stable output voltage, with keeping low power consumption and a high speed operation, if manufacturing processes and operational conditions of the LSI'S are varied. The level conversion circuit comprising a first input portion for receiving a first CMOS level signal as a differential signal at the CMOS level and a second CMOS level signal as an inverted signal of the first CMOS level signal, and outputting a first output current and a second output current based on these signals, a first conversion output portion for outputting a first PECL level signal as the PECL level differential signal and a second PECL level signal as an inverted signal of the first PECL level signal based on the first output current and the second output current from the first input portion, and a first current control portion for controlling the first output current and the second output current in the first conversion output portion by a first current control signal and a second current control signal so as to determine high level and low level in the first PECL level signal and the second PECL level signal.

REFERENCES:
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patent: 5311075 (1994-05-01), Usuki
patent: 5365127 (1994-11-01), Manley
Steyaert et al., "ECL-CMOS and CMOS-ECL Interface in 1.2-.mu.m CMOS for 150-MHz Digital ECL Data Transmission Systems", IEEE J. of Solid-State Circuits, vol. 26, No. 1, pp. 18-23 & 226-227, (1991).

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