CMOS parallel dynamic logic and speed enhanced static logic

Details CMOS parallel dynamic logic and speed enhanced static logic CMOS parallel dynamic logic and speed enhanced static logic

2001-05-07

2004-09-21

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000

Reexamination Certificate

active

06794903

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is CMOS logic. The invention finds particular use in CMOS microprocessor circuits.
BACKGROUND OF THE INVENTION
CMOS logic gates are fundamental components of microprocessor circuits. Much effort is still placed in the design of logic gate families. Static CMOS logic gates offer simple cascading, but exhibit slow response. Dynamic logic gates that have precharge and evaluation operations controlled by a clock signal often cannot be cascaded directly. A dynamic gate output precharged to a high logic level can cause improper charge operation of its next stage dynamic gate, leading to an erroneous evaluation result. If logic evaluation is through NMOS transistors of a gate, inputs for that gate should be precharged to a low logic level “L” to prevent unintended discharge. If PMOS, then precharge should be the high logic level “H” to prevent unintended charge up. If the input logic level is “X” during precharge and the output is denoted “Y”, gates may only be cascaded if Y(i)=X(j), where i<j and i,j denote the cascaded stage numbers.
Domino logic has been the logic family of choice for high-speed circuits in state-of-the-art processors such as Pentium Pro and Alpha. Domino logic circuits overcome the intrinsically slow nature of conventional static CMOS circuits, which is caused by the need for each gate to drive both NMOS and PMOS transistors. Domino logic circuits drive only NMOS transistors, thereby offering faster speed and smaller area compared to conventional static CMOS circuits.
The sole use of NMOS transistors is a drawback, however, that makes synthesis and general circuit design using a Domino logic family more complicated. Domino logic circuits have an inherently non-inverting nature, require strict timing constraints, and have a charge sharing problem. Domino logic with inverting and non-inverting outputs have been devised, but have their own set of problems.
NORA (NO RAce) circuits generate inverting logic only through strict cascading of NMOS and PMOS dynamic gates. Dual-rail logic circuits provide both inverting and non-inverting outputs, but occupy about twice the area of a standard domino gate. The extra power consumption of the dual-rail logic gates is also a serious drawback.
Some of these problems were addressed by Yee and Sechen, “Clock-Delayed Domino for Adder and Combinational Logic Design,” IEEE (Pub. No. 1063-6404/96)(1996). Clock-delayed domino (CD domino) eliminates the fundamental monotonic signal requirement by propagating a clock signal with controlled delay in parallel to the logic. However, the clock delay scheme is difficult to implement in practice. The clock delay must be large enough to allow evaluation of the slowest gates. Controlling this delay while satisfying the conflicting need for high speed logic is a difficult task. The delay is set equal to the worst case pull-down delay of the corresponding dynamic gate, with an added margin for differences in signal delay, coupling parasistics, and fabrication process variations. Minimizing the set delay is thus difficult.
CD domino is also sensitive to process variations. In addition, it requires additional circuitry that takes up area and consumes power. Specifically, extra precharge transistors and a keeper are used to reduce the effects of charge sharing, noise and coupling parasitics. Each CD domino gate typically requires a clock-delay logic device.
SUMMARY OF THE INVENTION
A new CMOS dynamic logic family is provided by this invention. The family is based on a parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including an NMOS and a PMOS transistor and parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family can provide NOR, NAND, OR, and AND. The family may also include BUF and INV. The BUF logic gate is realized with NMOS and PMOS transistors as evaluation transistors, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors.
Potential cascading difficulties in the parallel dynamic logic are solved by a speed enhanced skewed static (SSS) logic gate that is also provided by the invention. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined to form a plurality of separate gate inputs. An output from the gate is provided, and the sizes of PMOS transistors and NMOS transistors are skewed compared to conventional CMOS logic. Positive feedback transistors are connected to the output. A noise suppression transistor is also connected to the output. A precharge transistor connected to the positive feedback transistors is fed from a clock signal from an associated circuit. The speed enhanced skewed state logic gate is preferably used to solve cascading problems, as in CD domino or the present parallel dynamic logic, and the speed enhanced static gates may be used instead of clock delay. Also SSS logic can improve the speed of high fan-in gate or a gate with large output load.


REFERENCES:
patent: 5612638 (1997-03-01), Lev
Gin Yee and Carl Sechen, “Clock-Delayed Domino for Adder and Combinational Logic Design” in IEEE International Conference on Computer design, 1996, pp. 332-337.
Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, and Sung-Mo (Steve) Kang, “Parallel Dynamic Logic(PDL)with Speed-Enhanced Skewed Static(SSS)Logic”, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, Coordination Science Laboratory, May, 2000.

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