CMOS output pad driver with variable drive currents ESD protecti

Details CMOS output pad driver with variable drive currents ESD protecti CMOS output pad driver with variable drive currents ESD protecti

1993-07-14

1995-07-25

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 33, H03K 19003

Patent

active

054365783

ABSTRACT:
A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs. A photolithographic mask embodying a configurable circuit is provided to a designer who utilizes a CAD program to lay down polysilicon connections to select the drive transistors and disable the nonselected transistors.

REFERENCES:
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4745305 (1988-05-01), Crafts
patent: 4775809 (1988-10-01), Watanabe
patent: 4855623 (1989-08-01), Flaherty
patent: 4965469 (1990-10-01), Kondon et al.
patent: 4990802 (1991-02-01), Smooha
patent: 5220216 (1993-06-01), Woo
patent: 5285116 (1994-02-01), Thaik
patent: 5334885 (1994-08-01), Morris

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