CMOS output driver with slew rate control

Details CMOS output driver with slew rate control CMOS output driver with slew rate control

2001-02-20

2002-08-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C327S170000, C326S087000

Reexamination Certificate

active

06441653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to bus driver circuits, and more particularly to a CMOS output driver with slew rate control to ensure good signal integrity in a high-speed printed circuit board (PCB) system by reducing self-induced switching noise, transmission line effects generally attributable to PCB traces, and electromagnetic interference.
2. Description of the Prior Art
In modern high-speed PCB systems, fast bus drivers must have controlled output slew rates to ensure good signal integrity. Controlling the slew rate provides three advantages: 1) The self-induced Ldi/dt switching noise of the IC is reduced, 2) transmission line effects of the printed circuit board traces are reduced, and 3) electromagnetic interference is reduced.
FIG. 1
is a schematic diagram illustrating a simple standard CMOS output driver circuit without slew rate control
100
that is well known to those skilled in the art. The output transistors
102
,
104
are designed for high drive current capability and, as such, turn on with very fast slew rates.
Many slew rate control circuits have been proposed and implemented in the art. These well-known slew rate control circuits employ complex architectures such as delay lines, RC time constants, one-shots, multi-segmented output transistors, threshold-critical buffers, bias generators, and the like. One slew rate control circuit is disclosed in U.S. Pat. No. 5,877,647 to Vajapey et al., entitled I CMOS Output Buffer With Slew Rate Control, issued Mar. 2, 1999. The slew rate control circuit disclosed in the '647 patent employs multiple (or segmented) output transistors in which slew rate is controlled by relative sizing of the multiple output transistors. Further the slew rate control circuit disclosed in the '647 patent is controlled by timing the turn-on sequence of multiple output transistors by setting the threshold of feedback NAND or NOR gates. These gates have a large gain and result in an abrupt output impedance change when the threshold is crossed. These feedback NAND and NOR gates also have thresholds that are dependent upon the ratio of Pchannel to Nchannel drive strengths.
In view of the foregoing, a need exists for CMOS output driver with slew rate control that employs a single output transistor rather than multiple or segmented output transistors to control each output signal transition.
SUMMARY OF THE INVENTION
To meet the above and other objectives, the present invention provides an improved CMOS output driver having a DC feedback circuit that changes the output impedance of the driving transistors as the output voltage transition progresses. The output voltage slew rate is then controlled by limiting the gate voltages (node of Ng and Pg) of the output driver transistors during the transition.
In one aspect of the invention, a CMOS output driver with slew rate control employs a single output transistor, rather than multiple output transistors, to control slew rate during an output voltage transition.
In another aspect of the invention, a CMOS output driver with slew rate control employs a source follower feedback scheme to provide a smooth transition on the output transistor gate as the output signal transitions, resulting in low switching noise and reduced EMI.
In yet another aspect of the invention, a CMOS output driver with slew rate control integrates process compensation in gate driver transistors to minimize transmission line reflections and ripple.
In still another aspect of the invention, a CMOS output driver with slew rate control employs a resistor divider using matched resistors to limit and control output transistor gate drive during output signal transitions to reduce self-induced Ldi/dt noise.


REFERENCES:
patent: 4612466 (1986-09-01), Stewart
patent: 4725747 (1988-02-01), Stein et al.
patent: 4818901 (1989-04-01), Young et al.
patent: 4952818 (1990-08-01), Erdelyi et al.
patent: 5489862 (1996-02-01), Risinger et al.
patent: 5877647 (1999-03-01), Vajapey et al.
patent: 6087880 (2000-06-01), Takagi
patent: 6222403 (2001-04-01), Mitsuda
patent: 6236248 (2001-05-01), Koga

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