Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1994-03-14
1995-09-19
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Supply voltage level shifting
327534, H03K 190175
Patent
active
054518890
ABSTRACT:
A mixed mode buffer circuit 11 including a first input (12), a second input (13), and an output (14). A voltage exceeding a supply voltage of mixed mode buffer circuit 11 can be applied to the output (14) without latchup or an increase in leakage current. The mixed mode buffer includes an output transistor (24) of a first conductivity type having a first electrode coupled to the output (14), a control electrode coupled to the first input (12), a second electrode coupled for receiving the supply voltage, and a bulk electrode. A first transistor (19) biases the bulk electrode when the voltage at the output is within a first predetermined range. A first bulk bias circuit (28) biases the bulk electrode when the output voltage is within a second predetermined range. A second bulk bias circuit (27) and a second transistor (18) couples the voltage at the output to the bulk electrode and the control electrode respectively, when the output voltage exceeds the second predetermined range.
REFERENCES:
patent: 4782250 (1988-11-01), Adams et al.
patent: 4963766 (1990-10-01), Lundberg
patent: 5015889 (1991-05-01), Reay
patent: 5144165 (1992-09-01), Dhong et al.
patent: 5151619 (1992-09-01), Austin et al.
patent: 5160855 (1992-11-01), Dobberpuhl
Beckwith Deborah
Colbert Freeman D.
Heim Barry B.
Hu Paul T.
Morgan MonaLisa
Calogero Stephen
Hoshizaki Gary W.
Hudspeth David R.
Motorola Inc.
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