Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-06
2003-09-23
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C327S534000
Reexamination Certificate
active
06624660
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly relates to method and apparatuses for interfacing semiconductor devices with external circuitry.
BACKGROUND OF THE INVENTION
The field of semiconductor memory devices generally and complementary metal-oxide semiconductor (CMOS) devices in particular is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor memory devices of a variety of different types will continue to grow for the foreseeable future.
Semiconductor devices require input, output, and/or input/out (I/O) circuitry for interfacing them with external circuitry, including other semiconductor devices. In the context of a circuit for outputting signals from a semiconductor devices, the term “output driver” is often used. For example, on the input/output terminals of a semiconductor memory device, an output (or input/output) driver is required to present binary digital output signals on the I/O terminals. Most commonly, a logical low (binary “0”) signal is represented in a semiconductor by a substantially zero voltage. As semiconductor technologies have evolved, the standard voltage for representing a logical “high” (binary “1) signal has been being reduced from an earlier standard of 5 volts to an increasingly common 3.3 volts. For reasons relating to, among other factors, power consumption, thermal performance, speed, and device size, it is entirely possible that the standard voltage for representation of a logical high (binary “1”) voltage could be reduced even further as semiconductor technologies evolve.
The shift to lower operating voltages in semiconductor devices has not occurred all at once within the semiconductor industry. Hence, there has been an ongoing desire for semiconductor devices which are capable of recognizing a range of logical voltages, for example, recognizing either 1.8 volts or 2.5 volts as a logical high (binary “1”) voltage. Even for semiconductor devices intended to operate only at one operating voltage, however, care must be taken to ensure that the device can withstand an occasional or even sustained overdrive condition without adverse consequences. Those of ordinary skill in the art will understand that the term “overdrive condition” is used to refer to voltages or currents at an electrical node, such as at an input pad, which exceed specified levels, such as a manufacturer's specification of the “normal” operating parameters of a part. “Overdrive conditions” can be contrasted with what is typically referred to as a “normal operating conditions”, i.e., condition specified by a semiconductor device manufacturer to be within specified limits. By way of example, for an input/output pin on a semiconductor device specified for operation with a supply voltage of 3.3 volts, a voltage of greater than five volts present on that pad might be considered an overdrive condition.
Those of ordinary skill in the art will be familiar with some of the widely recognized and well-documented problems associated with overdrive conditions occurring at I/O terminals (and other electrical nodes) of semiconductor devices. One especially common problem is the potential for latch-up conditions resulting from overdrive conditions within a semiconductor device. Those of ordinary skill in the art will understand that a common type of “latch-up” condition is caused when parasitic (i.e., unintentional) conduction paths are created between otherwise separate semiconductor regions as a result of an overdriving of the I/O pad. Such conditions can create sustained current flow between adjacent semiconductor regions, causing the semiconductor circuitry to cease proper function or even to self-destruct.
Semiconductor I/O devices are especially susceptible to latch-up owing to their exposure to external conditions, including the application of external voltages or currents exceeding specified limits. A semiconductor input/output circuit commonly comprises a “pull-up” device and a “pull-down” device. The term “pull-up” device refers to the circuitry adapted to pull an output node to the desired logical high (binary “1”) voltage, e.g., 3.3 volts or 5 volts, whereas the term “pull-down” device refers to the circuitry adapted to pull an output node to a desired logical low (binary “0”) voltage (typically 0 voltages). In order to satisfy the performance requirements of modern semiconductor circuits, conventional data output buffers often employ N-channel metal oxide semiconductor (NMOS) transistors in both the pull-up and pull-down circuits. Perceived advantages of using NMOS pull-up transistors in an output driver rather than P-channel metal oxide semiconductor (PMOS) transistors include smaller size, and less susceptibility to latch-up. These considerations are discussed in U.S. Pat. No. 6,141,263 to Protzman, entitled “Circuit and Method for a High Transfer Rate Output Driver,” which patent is commonly assigned to the assignee of the present invention and is hereby incorporated by reference herein in its entirety.
On the other hand, there are also perceived advantages to using PMOS transistors in output drivers. One such advantage is switching speed, since it is generally understood that a PMOS pull-up transistor switches at a faster speed than an NMOS transistor, not requiring a boosted control signal on its gate. However, unlike an NMOS driver, a PMOS driver has the potential to increase a buffer circuit's susceptibility to cause latch-up of adjacent CMOS circuits. In common implementations of PMOS output drivers, when the I/O pad's voltage or current conditions exceed certain levels, a parasitic P+to N-well junction is forward-biased, and a parasitic P-N diode can be formed between the pad's P+ diffusion and the N+ diffusion guard ring. This results in heavy injected current into the N-well. This injected current is then capable of forward biasing other parasitic PNP structures, ultimately leading to the injection of hole current into the P substrate.
In a so-called “pumped substrate” design, where the substrate is not directly tied to ground but instead is negatively biased by a P-substrate charge pump, any large injection of hole current into the substrate can readily overwhelm the pump, making such a design highly susceptible to I/O-injected latch-up. The latch-up problem is potentially more severe in pumped substrate devices, because the typical latch-up prevention scheme of grounding the P-substrate with P+ guard rings cannot be utilized. The negative pump generator can only provide a limited amount of negative current to counter the positive current injected into the P-substrate or P-well. Latch-up occurs when the parasitic PN diode formed by the P-channel driver transistor and the V
cc
N+ guard ring biases the N-well to a high enough voltage to turn on the parasitic vertical PNP transistor connected between the P+ driver diffusion, the N-well, and the P-substrate. If enough hole current is injected into the P-substrate, then the local P-substrate voltage potential can increase to above V
diode
(the forward voltage of a PN diode). This increase in the P-substrate potential will forward-bias parasitic PN diodes of nearby V
ss
N+ active areas, resulting in the triggering of the parasitic PNPN latch-up devices between I/O and Vss or between the power supplies V
cc
and V
ss
.
Although there are many aspects of circuit design and layout that are important to the subject of latch-up, there are a few well-known basic features that can be incorporated into a CMOS device to reduce susceptibility to latch-up. Among the more important of these are design techniques that avoid the formation of parasitic bipolar transistors in CMOS circuitry.
For example, one technique that both decouples parasitic bipolar transistors
Chaine Michael D.
Li Wen
Ma Manny Kin
Chang Daniel
Cho James H.
Kress Hugh R.
Winstead Sechrest & Minick
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