CMOS output circuit with high speed high impedance mode

Details CMOS output circuit with high speed high impedance mode CMOS output circuit with high speed high impedance mode

1994-07-20

1996-02-06

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 17, 326 87, 326 88, H03K 1900, H03K 19094

Patent

active

054898595

ABSTRACT:
In an output circuit for outputting an output signal having a given potential level in response to a potential level of an input signal wherein the output signal is permitted to be in high impedance state in response to a first potential level of a reset control signal having first and second potential levels, the output circuit comprises a second control circuit for outputting a second output control signal in response to the input signal at the time when the reset control signal has the second potential level and also for outputting a third output control signal at the time delayed by a first time counting from the outputting of the second output control signal, the second control circuit having a function to stop the outputting of the second output control signal in response to the change of the potential of the reset control signal from its second potential level to its first potential level and also a function to stop the outputting of the third output control signal substantially at the same time as the stoppage of the outputting of the second output control signal or at the time delayed by a second time which is shorter than the first time, thereby permitting the output terminal to be in high impedance at high speed.

REFERENCES:
patent: 4757214 (1988-07-01), Kobayashi
patent: 4772812 (1988-09-01), Desmerais
patent: 4806798 (1989-02-01), Kanauchi
patent: 5121000 (1992-06-01), Naghsineh
patent: 5144161 (1992-09-01), Inaba
patent: 5220209 (1993-06-01), Seymour

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