CMOS output buffer having load independent slewing

Details CMOS output buffer having load independent slewing CMOS output buffer having load independent slewing

1997-12-02

1999-10-26

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 83, 326 17, 326 21, H03K 1903, H03K 1994

Patent

active

059735120

ABSTRACT:
n
A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage. The second half-circuit includes a second output transistor connected between the output node and the first voltage reference node, a third switching device connected from the gate of the second output transistor to the first voltage reference node, a fourth switching device connected from the gate of the second output transistor to a second node, a second current source connected from the second voltage reference node to the second node, and a second capacitor connected from the output node to the second node.

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